Patent application number | Description | Published |
20080222443 | Controller - The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device ( | 09-11-2008 |
20080228988 | METHOD FOR TRANSMITTING CONFIGURATION DATA VIA A CONFIGURATION DATA BUS IN A MEMORY ARRANGEMENT, CONFIGURATION DATA BUS STRUCTURE, MEMORY ARRANGEMENT, AND COMPUTER SYSTEM - A method transmits configuration data in a memory arrangement. The method includes controlling, with a control unit of the memory arrangement, data transmissions via a configuration data bus in the memory arrangement, the controlling including controlling transmitting configuration data of the memory arrangement for storing in at least two register units of the memory arrangement via the configuration data bus from the control unit to each of the at least two register units. The method includes storing, in the at least two register units, the configuration data. The at least two register units have a same bus address identifying the at least two register units on the configuration data bus. The method includes requesting, with the control unit, configuration data stored in the at least two register units. The method includes transmitting, under control of the control unit, the stored configuration data via the configuration data bus from only one of the at least two register units to the control unit. | 09-18-2008 |
20080229033 | Method For Processing Data in a Memory Arrangement, Memory Arrangement and Computer System - A method processes data in a memory arrangement. The method includes receiving and transmitting the data from the memory arrangement in the form of data packets according to a predefined protocol. The method includes distributing each received data packet to at least two separate data packet processing units. Each data packet processing unit is coupled to a portion of memory cells of the memory arrangement. The method includes processing, at each data packet processing unit, parts of the received data packets that relate to the portion of the memory cells the data packet processing unit is coupled to. The method includes generating a data packet to be transmitted including setting up, with each data packet processing unit, a part of the data packet to be transmitted. | 09-18-2008 |
20090016130 | MEMORY DEVICE AND METHOD OF TESTING A MEMORY DEVICE - In a method of testing a memory device, an output path of the memory device and an input path of the memory device are coupled to each other. A signal is transmitted, controlled by a test pattern, via the output path of the memory device. The signal is received via the input path of the memory device and evaluated. | 01-15-2009 |
20090073010 | DATA CONVERSION - A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams. | 03-19-2009 |
20140223050 | Receiver Architecture - In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to determine that a first output signal is a first symbol if a first received bus signal transitions from a first bus state to a second bus state and stays in the second bus state for less than a first predetermined period of time, and the first output signal is a second symbol if the first received bus signal transitions from the first bus state to the second bus state and stays in the second bus state for at least the first predetermined period of time. | 08-07-2014 |
20140355158 | SHUTDOWN PROTECTION FOR BUS LINE DRIVERS - An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch. | 12-04-2014 |
20140359190 | OVER-CURRENT DETECTION FOR BUS LINE DRIVERS - An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input. | 12-04-2014 |