| Patent application number | Description | Published |
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| 20080209167 | APPARATUS AND METHOD FOR ADAPTIVE MULTIMEDIA RECEPTION AND TRANSMISSION IN COMMUNICATION ENVIRONMENTS - The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions. | 08-28-2008 |
| 20080244197 | EXTERNAL MEMORY CONTROLLER NODE - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 10-02-2008 |
| 20080247443 | Method and system for implementing a system acquisition function for use with a communication device - A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. In another embodiment, a communication device having a system acquisition function is provided which includes the system acquisition module and a receiver configured to receive signals, where a plurality of configurable computational units are selectively configurable to implement the PN sequence generator. | 10-09-2008 |
| 20090037673 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 02-05-2009 |
| 20090037692 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 02-05-2009 |
| 20090037693 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 02-05-2009 |
| 20090055598 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 02-26-2009 |
| 20090103594 | Communications module, device, and method for implementing a system acquisition function - A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator. | 04-23-2009 |
| 20090104930 | Apparatus, module, and method for implementing communications functions - A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. In another embodiment, a communication device having a system acquisition function is provided which includes the system acquisition module and a receiver configured to receive signals, where a plurality of configurable computational units are selectively configurable to implement the PN sequence generator. | 04-23-2009 |
| 20090119480 | Method, System and Program for Developing and Scheduling Adaptive Integrated Circuitry and Corresponding Control or Configuration Information - A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes. | 05-07-2009 |
| 20090172137 | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements - The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes. | 07-02-2009 |
| 20090276582 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 11-05-2009 |
| 20090276583 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 11-05-2009 |
| 20090276584 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 11-05-2009 |
| 20090313482 | Apparatus, Method and System for Generating a Unique Hardware Adaptation Inseparable from Correspondingly Unique Content - The present invention includes an apparatus, method and system for generating a configuration of an adaptive circuit which is inseparable from selected content. Either the adaptive circuit or encrypted, selected content has a unique identifier. In one of the preferred method and system embodiments in which the adaptive circuit has the unique identifier, a request for the selected content is received, along with the unique identifier, such as by a network server. The selected content is then encrypted, based upon the unique identifier, to form encrypted content. Configuration information for the adaptive circuit, corresponding to the unique identifier and the encrypted content, is generated to form corresponding configuration information. A service provider, such as through a network server, transfers the encrypted content and the corresponding configuration information to the adaptive circuit having the unique identifier, which may then be configured for use of the selected content. As a consequence, the present invention creates adaptive hardware configurations which are uniquely coupled to the selected content. | 12-17-2009 |
| 20090325555 | System For Adapting Device Standars After Manufacture - A system for efficient sale of devices that comply with licensed standards. A preferred embodiment of the invention uses a generic, or highly adaptable, hardware device. The device can be adapted to adhere to a specific standard, e.g., code-division multiple access, time-division multiple access, etc., after manufacture such as at the point-of-sale to an end user, prior to distribution, or at some other point in a distribution and sales network. This allows manufacturers, retailers and end users to benefit from more competitive selection of standardized communication, data and other formats. Reduction of manufacturing costs and elimination of shipping, or other transfer and storage costs, is also realized. | 12-31-2009 |
| 20100002100 | System for adapting device standards after manufacture - The present invention provides a digital imaging apparatus having an optical sensor, an analog-to-digital converter, a plurality of computational elements, and an interconnection network. The optical sensor converts an object image into a detected image, which is then converted to digital image information by the analog-to-digital converter. The plurality of computational elements includes a first computational element having a first fixed architecture and a second computational element having a second, different fixed architecture. The interconnection network is capable of providing a processed digital image from the digital image information by configuring and reconfiguring the plurality of computational elements for performance of a plurality of different imaging functions. The invention may be embodied, for example, as a digital camera, a scanner, a printer, or a dry copier. | 01-07-2010 |
| 20100149091 | Media Action Script Acceleration Method - Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary method comprises: converting a plurality of descriptive elements into a plurality of operational codes which at least partially control at least one processor circuit; and using at least one processor circuit, performing one or more operations corresponding to an operational code to generate pixel data for the graphical image. Another exemplary method for processing a data file which has not been fully compiled to a machine code and comprising interpretable descriptions of the graphical image in a non-pixel-bitmap form, comprises: separating the data file from other data; parsing and converting the data file to a plurality of hardware-level operational codes and corresponding data; and performing a plurality of operations in response to at least some hardware-level operational codes to generate pixel data for the graphical image. Exemplary embodiments also may be performed automatically by a system comprising one or more computing devices. | 06-17-2010 |
| 20100149189 | Media Action Script Acceleration Apparatus - Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory to store corresponding data; a first processor to separate the action script from other data; and a second processor to convert a plurality of descriptive elements of the action script into a plurality of operational codes, and to perform an operation corresponding to an operational code of the plurality of operational codes using the corresponding data to generate pixel data for the graphical image. In exemplary embodiments the second processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields. | 06-17-2010 |
| 20100149192 | Media Action Script Acceleration System - Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary system comprises: a network I/O interface; a frame buffer; a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields. | 06-17-2010 |
| 20100149215 | Media Action Script Acceleration Apparatus, System and Method - Exemplary apparatus, method, and system embodiments provide for processing an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes; and second circuitry configured to execute the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image. Exemplary embodiments may further include third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data, and fourth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields. | 06-17-2010 |
| 20100153692 | Media Action Script Acceleration Apparatus - Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields. | 06-17-2010 |
| 20100159910 | APPARATUS AND METHOD FOR ADAPTIVE MULTIMEDIA RECEPTION AND TRANSMISSION IN COMMUNICATION ENVIRONMENTS - The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions. | 06-24-2010 |
| 20100161775 | APPARATUS AND METHOD FOR ADAPTIVE MULTIMEDIA RECEPTION AND TRANSMISSION IN COMMUNICATION ENVIRONMENTS - The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions. | 06-24-2010 |
| 20100161940 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 06-24-2010 |
| 20100191961 | METHOD AND SYSTEM ACHIEVING INDIVIDUALIZED PROTECTED SPACE IN AN OPERATING SYSTEM - Aspects for achieving individualized protected space in an operating system are provided. The aspects include performing on demand hardware instantiation via an ACE (an adaptive computing engine), and utilizing the hardware for monitoring predetermined software programming to protect an operating system. | 07-29-2010 |
| 20100220706 | Apparatus, Module, And Method For Implementing Communications Functions - A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. In another embodiment, a communication device having a system acquisition function is provided which includes the system acquisition module and a receiver configured to receive signals, where a plurality of configurable computational units are selectively configurable to implement the PN sequence generator. | 09-02-2010 |
| 20100293356 | METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions. | 11-18-2010 |
