Patent application number | Description | Published |
20110310992 | SYSTEMS, METHODS, AND COMPUTER READABLE MEDIA FOR FRACTIONAL PRE-EMPHASIS OF MULTI-MODE INTERCONNECT - Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated. Pre-emphasize each analog signal output according to the respective pre-emphasis signal, where the analog signal is pre-emphasized for a fraction of a period that is less than the entire period. | 12-22-2011 |
20120175696 | MULTILAYER FLOATING GATE FIELD-EFFECT TRANSISTOR (FET) DEVICES AND RELATED METHODS - Multilayer floating gate field-effect transistor (FET) devices and related methods are provided. A multilayer floating gate FET device can include a first floating gate separated via a first dielectric layer from a channel of the device and a second floating gate separated via a second dielectric layer from the first floating gate. The second dielectric layer between the first floating gate and the second floating gate permits a redistribution of charge between the first and second floating gates from one of the floating gates to the other when under the influence of a first electrical field from a first voltage. In some embodiments, a redistribution of charge between the first and second floating gates with electrons being supplied through a channel to the first and second floating gates can occur when under the influence of a second electrical field from a second voltage that is greater than the first voltage. | 07-12-2012 |
20130069709 | AC POWERED LOGIC CIRCUITS AND SYSTEMS INCLUDING SAME - AC powered logic circuits and systems including same are disclosed. According to one aspect, a system including a logic circuit powered using an alternating current (AC) power source includes at least one supply transistor connected to receive voltages of opposite phases from an AC power source such that the at least one supply transistor is strongly on during a first phase of the voltage of the AC power source and is strongly off during a second phase opposite the first phase of the voltage of the AC power source and at least one logic circuit connected to be powered by the AC power source through the at least one supply transistor and producing an output at an output terminal responsive to an input received at an input terminal. | 03-21-2013 |
20130168674 | Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated Circuits - A three-dimensional integrated circuit (3D-IC) includes a stack of semiconductor wafers, each of which includes a substrate and a device layer. Programmable components, such as memory arrays or logic circuits, are formed within the device layers. Some of the programmable components are redundant, and can be substituted for defective components by programming passive memory elements in a separate conductive layer provided for this purpose. The separate conductive layer is devoid of active devices, and is therefore relatively reliable and inexpensive. | 07-04-2013 |
20130176763 | STACKED MEMORY WITH REDUNDANCY - A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. | 07-11-2013 |
20130300498 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR LOW POWER MULTIMODE INTERCONNECT FOR LOSSY AND TIGHTLY COUPLED MULTI-CHANNEL - Methods, systems, and computer readable media for low power multimode interconnect for lossy and tightly coupled multi-channel are disclosed. According to one aspect, a system for low power multimode interconnect includes a receiver for receiving a plurality of input signals that have been encoded by a multimode encoding equation to have voltage levels according to the multimode encoding equation and for decoding the received signals according to a multimode decoding equation to produce binary data as output, wherein the receiver includes a set of frequency-compensated amplifiers for emphasizing high-frequency components of the received input signals and a set of latches for receiving amplified signals from the frequency-compensated amplifiers and for decoding the amplified signals according to the multimode decoding equation to produce binary data as output. | 11-14-2013 |
20130314102 | DELAY FAULT TESTING FOR CHIP I/O - An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input. | 11-28-2013 |
20130314291 | MILLIMETER SCALE THREE-DIMENSIONAL ANTENNA STRUCTURES AND METHODS FOR FABRICATING SAME - Millimeter scale three dimensional antenna structures and methods for fabricating such structures are disclosed. According to one method, a first substantially planar die having a first antenna structure is placed on a first surface. A second substantially planar die having at least one conductive element is placed on a second surface that forms an oblique angle with the first surface. The first and second dies are mechanically coupled to each other such that the first die and the first antenna structure extend at the oblique angle to the second die. | 11-28-2013 |
20140003549 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR ASYMMETRIC MULTIMODE INTERCONNECT | 01-02-2014 |
20140321186 | STACKED MEMORY WITH REDUNDANCY - A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information. | 10-30-2014 |
20140376364 | TEMPORAL REDUNDANCY - A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate. | 12-25-2014 |