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| 20100330583 | Compositions and methods for identification of PARP function, inhibitors, and activators - The invention provides nucleic acids encoding PARP fusion proteins, PARP fusion proteins, antibodies that bind to one or more of these PARP fusion proteins, and transgenic cells expressing one or more PARP fusion proteins. The invention also provides methods for identifying an agent as a specific PARP inhibitor or activator requiring contacting one or more PARP fusion proteins with a labeled nicotinamide adenine dinucleotide substrate and the agent and measuring the amount of labeled of ADP-ribose covalently attached to the one or more PARP fusion proteins. The invention also provides methods for identifying an agent that specifically binds to one or more PARP fusion proteins and methods for quantitating the level of one or more PARP proteins in a sample. | 12-30-2010 |
| 20110097328 | METHODS AND COMPOSITIONS FOR INCREASING THE ACTIVITY OF INHIBITORY RNA - The invention provides methods for increasing the activity of an inhibitory RNA (RNAi) in a subject requiring administering one or more poly-ADP-ribose polymerase (PARP) inhibitors and/or one or more PARG activators to the subject. The invention also provides methods for increasing the activity of an inhibitory RNA in a cell or cell population requiring contacting a cell or cell population with one or more PARP inhibitors and/or one or more PARG activators. The invention further provides compositions and kits containing one or more PARP inhibitors and/or one or more PARG activators. | 04-28-2011 |
| 20110097329 | COMPOSITIONS AND METHODS FOR TREATING CANCER AND MODULATING STRESS GRANULE FORMATION - The invention provides methods for treating or decreasing the likelihood of developing a stress-granule related disorder and/or cancer by administering one or more poly-ADP-ribose polymerase (PARP) inhibitors, one or more PARP activators, one or more poly-ADP-ribose glycosylase (PARG) activators, and/or one or more poly-ADP-ribose glycohydrolase ARH3 activators. The invention also provides corresponding methods of decreasing stress granule formation and/or proliferation in a cell or a population of cells. The invention further provides methods of increasing the number of stress granules and proliferation in a cell or a population of cells by administering one or more PARP activators, one or more PARP inhibitors, one or more PARG inhibitors, and/or one or more ARH3 inhibitors. The invention also provides methods for screening for agents for treating or decreasing the likelihood of developing a stress granule-related disorder or cancer, and methods for determining the propensity for developing a stress granule-related disorder or cancer, as well as compositions and kits containing one or more PARP inhibitors, one or more PARP activators, one or more PARG activators, and one or more ARH3 activators. | 04-28-2011 |
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| 20090106714 | METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD - Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design. | 04-23-2009 |
| 20100207208 | NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME - A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region. | 08-19-2010 |
| 20100297816 | NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME - A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region. | 11-25-2010 |
| 20110082680 | COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS - A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis. | 04-07-2011 |
| 20110307846 | METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD - Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design. | 12-15-2011 |
| 20110309332 | EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS - A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks. | 12-22-2011 |
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| 20100295021 | Single Gate Inverter Nanowire Mesh - Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided. | 11-25-2010 |
| 20100295022 | Nanowire Mesh FET with Multiple Threshold Voltages - Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels. | 11-25-2010 |
| 20110031473 | Nanomesh SRAM Cell - Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels. | 02-10-2011 |
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| 20090245961 | MACHINING APPARATUS - A machining apparatus includes a support frame, first and second workbenches, and a tool-mounting unit. The support frame includes a first horizontal frame part, and a second horizontal frame part disposed above the first horizontal frame part. The first and second workbenches are mounted slidably on the first horizontal frame part of the support frame, and is slidable relative to the support frame in a first horizontal direction. The tool-mounting unit is mounted slidably on the second horizontal frame part of the support frame, and is slidable relative to the support frame in a second horizontal direction transverse to the first horizontal direction. | 10-01-2009 |
| 20100066291 | METHOD AND MODULE FOR CONTROLLING ROTATION OF A MOTORIZED SPINDLE - In a method and module for controlling rotation of a motorized spindle driven by a driving unit, a sensing unit is adapted for sensing vibration of the spindle and generates a voltage signal corresponding to the vibration of the spindle. A processing unit is coupled to the sensing unit for receiving the voltage signal therefrom, and outputs a control signal corresponding to the voltage signal upon detecting that the voltage signal is greater than a reference voltage corresponding to a predetermined vibration level of the spindle, such that the driving unit adjusts a rotation speed of the spindle in response to the control signal from the processing unit. | 03-18-2010 |
| 20100119319 | PROCESSING MACHINE - A processing machine includes a machine bed, a spindle seat, a sliding rail unit, and a driving unit. The sliding rail unit is disposed between the machine bed and the spindle seat. The driving unit is used for driving the spindle seat to move within a slot in the machine bed, and includes a threaded rod journalled on a junction between a bottom wall surface and a lateral wall surface of the machine bed, and a nut member disposed fixedly on a junction between a bottom surface and a lateral side surface of the spindle seat and engaging the threaded rod. | 05-13-2010 |
| 20100249982 | DISPLACEMENT COMPENSATION CONTROL METHOD AND MODULE FOR AN OBJECT MOUNTED MOVABLY ON A DRIVING ROD UNIT - In a displacement compensation control method and module for an object mounted movably on a driving rod unit and movable between first and second positions relative to the driving rod unit during processing, a detecting unit determines a displacement amount of a free end of the driving rod unit from a reference position in an axial direction of the driving rod unit as a result of thermal deformation of the driving rod unit during high-speed rotation. A control unit controls the driving rod unit to rotate based on the displacement amount so that the object moves between first and second compensation positions relative to the driving rod unit. A distance between the first position and the first compensation position, and a distance between the second position and the second compensation position are equal to the displacement amount. | 09-30-2010 |
