Patent application number | Description | Published |
20120173792 | Controller and Method for Performing Background Operations - The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed. | 07-05-2012 |
20120331207 | Controller, Storage Device, and Method for Power Throttling Memory Operations - The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed. | 12-27-2012 |
20120331282 | APPARATUS AND METHODS FOR PEAK POWER MANAGEMENT IN MEMORY SYSTEMS - Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system. | 12-27-2012 |
20130054871 | CONTROLLER WITH EXTENDED STATUS REGISTER AND METHOD OF USE THEREWITH - The embodiments described herein provide a controller with an extended status register and a method of use therewith. In one embodiment, a controller is provided with a first interface through which to communicate with a host and a second interface through which to communicate with a plurality of flash memory devices. The controller also comprises a status register, an extended status register, and a processor. The processor is operative to store, in the extended status register, status information of a plurality of events in time across the plurality of flash memory devices. The extended status register stores event status information, whereas the ONFI status register stores command status information. In response to a request from the host, the processor sends the status information of the plurality of events to the host for analysis. | 02-28-2013 |
20130159601 | Controller and Method for Virtual LUN Assignment for Improved Memory Bank Mapping - A controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies, each having a respective plurality of memory blocks, some of which are good and some of which are bad. The controller determines a number of good blocks in each memory die. Based on the determined number of good blocks in each memory die, the controller selects a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package. The controller then creates a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies. | 06-20-2013 |
20130173842 | Adaptive Logical Group Sorting to Prevent Drive Fragmentation - A method and system are disclosed for controlling the storage of data in a storage device to reduce fragmentation. The method may include a controller of a storage device receiving data for storage in non-volatile memory and determining if a threshold amount of data has been received. When the threshold amount of data is received, the non-volatile memory is scanned for sequentially numbered logical groups of data previously written in noncontiguous locations in the non-volatile memory. When a threshold amount of such sequentially numbered logical groups is found, the controller re-writes the sequentially numbered logical groups of data contiguously into a new block. The system may include a storage device with a controller configured to perform the method noted above, where the thresholds for scanning the memory for fragmented data and removing fragmentation by re-writing the fragmented data into new blocks may be fixed or variable. | 07-04-2013 |
20130173846 | Controller and Method for Memory Aliasing for Different Flash Memory Types - A controller and method for memory aliasing for different flash memory types are presented. In one embodiment, a controller is presented having one or more interfaces through which to communicate with a plurality of memory dies, wherein at least one of the memory dies is of a different memory type than the other memory dies. The controller also has an interface through which to communicate with a host, wherein the interface only supports commands for a single memory types. The controller further contains a processor that is configured to receive a logical address and a command from the host, determine which memory die is associated with the logical address, and translate the command received from the host to a form suitable for the memory type of the memory die associated with the logical address. | 07-04-2013 |
20130173848 | Controller and Method for Using a Transaction Flag for Page Protection - A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command. | 07-04-2013 |
20130265825 | SYSTEM AND METHOD FOR MICRO-TIERING IN NON-VOLATILE MEMORY - In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP. | 10-10-2013 |
20140237167 | Apparatus and Methods for Peak Power Management in Memory Systems - Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system. | 08-21-2014 |
20140289458 | SYSTEM AND METHOD FOR MICRO-TIERING IN NON-VOLATILE MEMORY - In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP. | 09-25-2014 |
20140325131 | Controller and Method for Performing Background Operations - The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed. | 10-30-2014 |