Patent application number | Description | Published |
20080219390 | Receiver Circuit - A thermometer code to sign and magnitude converter that is particularly useful in a flash ADC is provided. This comprises two conversion units. The first is a thermometer code to Gray code converter and the second a Gray code to sign and magnitude converter. Preferably, the Gray code is of a kind that has a sign bit and has the other bits symmetrically disposed about zero. This form is easily converted to a sign and magnitude code, which is advantageous as it reduces the latency of the converter, which is particularly useful at high data rates. | 09-11-2008 |
20090034311 | LOW POWER TERNARY CONTENT-ADDRESSABLE MEMORY (TCAM) - An integrated circuit ( | 02-05-2009 |
20100163948 | Integrated Circuit Having Efficiently Packed Decoupling Capacitors - An integrated circuit includes a substrate having a semiconducting surface ( | 07-01-2010 |
20120246400 | METHOD AND APPARATUS FOR PACKET SWITICHING - A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules. | 09-27-2012 |
20130125078 | Interactive Routing Editor with Symbolic and Geometric Views for Integrated Circuit Layout - An automated system, and method of operating the same, for interactively routing interconnections in a layout of an integrated circuit. Interconnections among subchips in the integrated circuit, specified by a netlist, are displayed by the system by way of airlines. The system provides a symbolic view of the bus, showing a representative wire of the bus, such as that associated with the least-significant or most-significant bit position in the bus. The physical routing of the representative wire is interactively defined, using orthogonal wire segments in selected conductor levels. Bus properties, for example including bit pitch, wire pitch, LSB/MSB, and a direction of expansion, are associated with the routing data for each segment of the representative wire. The combination of the routing data and the bus property data enable building of the entire bus from the interactive routing of the representative wire in the symbolic view. | 05-16-2013 |
20130205274 | System and Method for Integrated Circuit Layout Editing with Asymmetric Zoom Views - An automated system, and method of operating the same, for assisting the layout of components and the routing of conductors in a layout of an integrated circuit. An asymmetric zoom command is provided, by way of which the user can magnify the current view of a portion of the layout in one dimension while maintaining the original magnification in the orthogonal dimension. The commands can be conveyed by keystrokes, or by a command in combination with a drawn rectangle indicating the extent of the asymmetric zoom magnification. Both asymmetric zoom-in and asymmetric zoom-out are supported. | 08-08-2013 |
20140219294 | ROTATE-MASK-MERGE AND DEPOSIT-FIELD INSTRUCTIONS FOR PACKET PROCESSING - In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros. | 08-07-2014 |
20140241358 | PACKET PROCESSING MATCH AND ACTION UNIT WITH A VLIW ACTION ENGINE - An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word. | 08-28-2014 |
20140241359 | PACKET PROCESSING VLIW ACTION UNIT WITH OR-MULTI-PORTED INSTRUCTION MEMORY - An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result. | 08-28-2014 |
20140241361 | PACKET PROCESSING MATCH AND ACTION UNIT WITH CONFIGURABLE MEMORY ALLOCATION - A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory. | 08-28-2014 |
20140241362 | PACKET PROCESSING MATCH AND ACTION UNIT WITH CONFIGURABLE BIT ALLOCATION - A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories. | 08-28-2014 |
20140244966 | PACKET PROCESSING MATCH AND ACTION UNIT WITH STATEFUL ACTIONS - A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory. | 08-28-2014 |
20140268971 | TCAM WITH EFFICIENT RANGE SEARCH CAPABILITY - An embodiment of the invention includes a ternary content addressable memory (TCAM) that has input search data bits, TCAM words and range search input data bits. Each TCAM word is operable to store a match pattern and provide a match output. The match output indicates a match when the match pattern of the TCAM word matches the TCAM input search data bits. The range search input data bits are separated into groups. Each group has a bit width N where N is the number of range search input data bits. For the match pattern in each group, there is a Boolean function that uses the N range of search input data bits. (2 | 09-18-2014 |
20140268972 | TCAM WITH EFFICIENT MULTIPLE DIMENSION RANGE SEARCH CAPABILITY - An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the TCAMs includes a plurality of words, stores TCAM match entries and outputs a TCAM match signal for each word in the plurality of words. The first vector includes first TCAM group enable register bits. An enabling value on the first TCAM register bit indicates that the first TCAM match signal and the neighboring first TCAM match are in the same TCAM group. The TCAM match-merge unit receives the first TCAM match signal from each of the words and the first vector and outputs a first TCAM group match signal for each of the words. The TCAM match-merge unit outputs a match indication when any of the TCAM match signals indicate a match and outputs a mismatch when none of the TCAM match signals match. | 09-18-2014 |
20140328180 | STRUCTURE FOR IMPLEMENTING OPENFLOW ALL GROUP BUCKETS USING EGRESS FLOW TABLE ENTRIES - An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment. | 11-06-2014 |
20140328344 | PACKET PROCESSING MATCH AND ACTION PIPELINE STRUCTURE WITH DEPENDENCY CALCULATION REMOVING FALSE DEPENDENCIES - An embodiment of the invention includes a plurality of tables in a hardware network for performing packet processing. Each table in the plurality of tables includes a table declaration. The table declaration includes a first set of fields used for input matching and a second set of fields used as inputs for action processing. A first table is selected from the plurality of tables. Successor tables to the first table are selected from the plurality of tables. There is a third set of fields for each successor table of the successor tables. The contents of the third set of fields are output fields where the output fields are modified by the first table when a next table of the first table is the successor table of the first table. | 11-06-2014 |
20140334489 | OPENFLOW MATCH AND ACTION PIPELINE STRUCTURE - An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage. | 11-13-2014 |