Patent application number | Description | Published |
20090154249 | SENSE AMPLIFIER FOR LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS - A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load. | 06-18-2009 |
20100054031 | COLUMN DECODER FOR NON-VOLATILE MEMORY DEVICES, IN PARTICULAR OF THE PHASE-CHANGE TYPE - A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage. | 03-04-2010 |
Patent application number | Description | Published |
20080285359 | Level-shifter circuit and memory device comprising said circuit - A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second circuit adapted to transfer the preset voltage level to a third circuit connected to a preset negative voltage value. The third circuit is connected to a further voltage at a positive or nil level and is adapted to supply an output voltage to the preset negative level or to the positive or nil level. | 11-20-2008 |
20110157972 | FTP MEMORY DEVICE PROGRAMMABLE AND ERASABLE AT CELL LEVEL - An embodiment of non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory includes at least one sector of a plurality of memory cells; each sector includes a storage region of a first type of conductivity and a further storage region of a second type of conductivity. Each memory cell includes a first region and a second region of the second type of conductivity, which are formed in the storage region for defining a storage transistor of floating gate MOS type of the first type of conductivity; the memory cell likewise includes a further first region and a further second region of the first type of conductivity, which are formed in the further storage region for defining a further storage transistor of floating gate MOS type of the second type of conductivity. The memory cell also includes a common floating gate of the storage transistor and the further storage transistor. The memory device further includes programming means for programming each memory cell individually by programming the corresponding floating gate through the corresponding storage transistor, and erasing means for erasing each memory cell individually by erasing the corresponding floating gate through the corresponding further storage transistor. | 06-30-2011 |
20110157975 | FTP MEMORY DEVICE WITH PROGRAMING AND ERASING BASED ON FOWLER-NORDHEIM EFFECT - An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are connected in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate. | 06-30-2011 |
20110157977 | FTP MEMORY DEVICE WITH SINGLE SELECTION TRANSISTOR - An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate. An embodiment, the memory device further includes means for applying a first programming voltage to the first wells and a second programming voltage to the control gates of a subset of the memory cells including at least one memory cell to be programmed (with a difference between the first programming voltage and the second programming voltage that is capable of injecting electric charge into the floating gate of each memory cell to be programmed), for applying the first programming voltage to the third region of each memory cell to be programmed, and for applying a third programming voltage (3.5V) comprised between the first programming voltage and the second programming voltage to the third region of each memory cell of the subset not to be programmed (with a difference between the first programming voltage and the third programming voltage that inhibits the injection of electric charge into the corresponding floating gate). | 06-30-2011 |
20140036564 | NON-VOLATILE MEMORY DEVICE WITH CLUSTERED MEMORY CELLS - An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row. | 02-06-2014 |
20140112080 | IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY - An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. In an embodiment, a corresponding method includes the following steps: selecting at least one of the sectors, determining an indication of the number of memory cells in the programmed state and an indication of the number of memory cells in the erased state of the selected sector, and identifying the condition of the selected sector according to a comparison between the indication of the number of memory cells in the programmed state and the indication of the number of memory cells in the erased state. | 04-24-2014 |
20150212880 | ERROR CORRECTION IN DIFFERENTIAL MEMORY DEVICES WITH READING IN SINGLE-ENDED MODE IN ADDITION TO READING IN DIFFERENTIAL MODE - A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word. | 07-30-2015 |
20150228338 | System and Method for Phase Change Memory - According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data. | 08-13-2015 |
20150235686 | System and Method for a Level Shifting Decoder - According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer. | 08-20-2015 |