Patent application number | Description | Published |
20100305227 | Protein-Containing Foams, Manufacture and Use Thereof - The invention relates generally to protein-containing polyurethane foams, methods and compositions for making the polyurethane foams, and articles comprising the polyurethane foams. | 12-02-2010 |
20100310877 | Protein-Containing Emulsions and Adhesives, and Manufacture and Use Thereof - This invention provides emulsions and adhesives comprising proteins that can be isolated from a variety of sources including renewable plant biomass, and methods of making and using such emulsions and adhesives. | 12-09-2010 |
20110120645 | ENERGY-ACTIVATED ROOM TEMPERATURE-PUMPABLE POLYMER COMPOSITIONS AND DEVICES FOR ACTIVATING AND DISPENSING THE SAME - Energy-activated room temperature-pumpable polymer compositions, devices for activating and processing the same into solid cellular or non-cellular polymeric materials that can be used as adhesives, sealants, coatings or gasket materials, and methods of making and using the same. The compositions according to the invention include solid particles that include one or more polymers, which are emulsified, dispersed or suspended in a liquid carrier together with at least one processing aid, such as a reactive blowing agent, a low molecular weight surfactant, a high molecular weight surfactant, one or more compounds found in latex paint, starch, cellulosic derived products and combinations of two or more thereof. The processing aids provide various benefits including, for example, reduced density, improved process hygiene, improved foam stability, faster bonding times and/or lower processing temperatures. | 05-26-2011 |
20110311833 | Protein-Containing Adhesives, and Manufacture and Use Thereof - The invention provides protein adhesives and methods of making and using such adhesives. The protein adhesives contain ground plant meal or an isolated polypeptide composition obtained from plant biomass. | 12-22-2011 |
20130065012 | PROTEIN-CONTAINING ADHESIVES, AND MANUFACTURE AND USE THEREOF - The invention provides protein adhesives and methods of making and using such adhesives. One type of protein adhesive described herein contains lignin and ground plant meal or an isolated polypeptide composition obtained from plant biomass. Other types of protein adhesives described herein contain a plant protein composition and either a hydroxyaromatic/aldehyde, urea/aldehyde, or amine/aldehyde component. | 03-14-2013 |
20140178695 | PROTEIN-CONTAINING EMULSIONS AND ADHESIVES, AND MANUFACTURE AND USE THEREOF - This invention provides emulsions and adhesives comprising proteins that can be isolated from a variety of sources including renewable plant biomass, and methods of making and using such emulsions and adhesives. | 06-26-2014 |
20140235737 | PROTEIN-CONTAINING FOAMS, MANUFACTURE AND USE THEREOF - The invention relates generally to protein-containing polyurethane foams, methods and compositions for making the polyurethane foams, and articles comprising the polyurethane foams. | 08-21-2014 |
20150044483 | PROTEIN-CONTAINING ADHESIVES, AND MANUFACTURE AND USE THEREOF - The invention provides protein adhesives containing certain additives and methods of making and using such adhesives. The protein adhesives contain ground plant meal or an isolated polypeptide composition obtained from plant biomass in combination with certain additives, such as an exfoliated clay or partially exfoliated clay. | 02-12-2015 |
20150203730 | PROTEIN-CONTAINING ADHESIVES, AND MANUFACTURE AND USE THEREOF - The invention provides protein adhesives and methods of making and using such adhesives. The protein adhesives contain ground plant meal or an isolated polypeptide composition obtained from plant biomass. | 07-23-2015 |
20150267095 | PROTEIN ADHESIVES CONTAINING AN ANHYDRIDE, CARBOXYLIC ACID, AND/OR CARBOXYLATE SALT COMPOUND AND THEIR USE - The invention provides protein adhesives, and methods of making and using such adhesives. The protein adhesives contain a protein-bonding agent and plant protein composition, such as an isolated water-soluble protein fraction or ground plant meal obtained from plant biomass. The protein-bonding agent can be an anhydride compound, carboxylic acid compound, carboxylate salt compound, or combinations thereof. The protein adhesives are useful in bonding together lignocellulosic materials and other types of materials. | 09-24-2015 |
Patent application number | Description | Published |
20080244473 | Modifying Integrated Circuit Designs to Achieve Multiple Operating Frequency Targets - A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions. | 10-02-2008 |
20090281772 | SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS - One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report. | 11-12-2009 |
20100026378 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage. | 02-04-2010 |
20100037188 | SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage. | 02-11-2010 |
20110022996 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS - Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool. | 01-27-2011 |
20110022998 | METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD - Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor. | 01-27-2011 |
20110023004 | ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLTAGE SCALING, ANALYZING THE BENEFITS AND AN APPARATUS THEREFOR - Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining. | 01-27-2011 |
20110307852 | SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS - One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report. | 12-15-2011 |
20120011484 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED TIMING-REALIZABLE CLOCK-INSERTION DELAYS AND INTEGRATED CIRCUIT DESIGN TOOLS - A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool. | 01-12-2012 |
20120095746 | NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW - A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget. | 04-19-2012 |
20120174048 | METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD - Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies. | 07-05-2012 |
20120221995 | SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE DYNAMIC POWER IN AN ELECTRONIC CIRCUIT AND AN APPARATUS INCORPORATING THE SAME - A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed. | 08-30-2012 |
20130055175 | SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist. | 02-28-2013 |
20140059505 | METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CORRECT-BY-CONSTRUCTION PROGRESSIVE MODELING AND AN APPARATUS EMPLOYING THE METHOD - Methods of designing an integrated circuit and an apparatus for designing an integrated circuit are disclosed herein. In one embodiment, a method includes: (1) generating a block model of the integrated circuit according to a first timing budget, (2) developing a top level implementation of the integrated circuit according to the first timing budget, (3) determining a second timing budget for the integrated circuit based on the block model and (4) modifying the block model and the top level implementation employing the second timing budget to provide a progressive block model and a modified top level implementation. | 02-27-2014 |
Patent application number | Description | Published |
20130036393 | NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW - A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block. | 02-07-2013 |
20130104096 | SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS - One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage. | 04-25-2013 |
20130339912 | HIERARCHICAL DESIGN FLOW GENERATOR - A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion. | 12-19-2013 |
20140131854 | MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS - One aspect provides an integrated circuit (IC) multi-chip packaging assembly, comprising a first IC chip having packaging substrate contacts and bridging block contacts, a second IC chip having packaging substrate contacts and bridging block contacts, and a bridging block partially overlapping the first and second IC chips and having interconnected electrical contacts on opposing ends thereof that contact the bridging block contacts of the first IC chip and the second IC chip to thereby electrically connect the first IC chip to the second chip. | 05-15-2014 |
20140298277 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) synthesizing a netlist from the functional IC design that meets the target clock rate, (4) determining a performance/power ratio from the netlist, (5) attempting to increase the performance/power ratio by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, and (6) implementing a layout of the IC from the netlist. | 10-02-2014 |
Patent application number | Description | Published |
20100063138 | NOVEL SUBSTITUTED SULFAMIDE DERIVATIVES - The present invention is directed to novel substituted sulfamide derivatives, pharmaceutical compositions containing said derivatives and the use of said derivatives form in the treatment of anxiety and related disorders; bipolar depression and mania; depression; epilepsy and related disorders; epileptogenesis; glucose related disorders; lipid related disorders; migraine; obesity; pain; substance abuse and as neuroprotective agents. The present invention is further directed to a process for the preparation of the novel substituted sulfamide derivatives. | 03-11-2010 |
20110105562 | ALKYNYL DERIVATIVES USEFUL AS DPP-1 INHIBITORS - The present invention is directed to novel alkynyl derivatives, pharmaceutical compositions containing them and their use in the treatment of disorders and conditions modulated by DPP-1. | 05-05-2011 |
20110152287 | SUBSTITUTED BENZOTHIAZOLE AND BENZOXAZOLE DERIVATIVES USEFUL AS INHIBITORS OF DPP-1 - The present invention is directed to substituted benzothiazole and benzoxazole derivatives, pharmaceutical compositions containing them and their use in the treatment of disorders and conditions modulated by DPP-1. | 06-23-2011 |
20110224209 | 4,4-DISUBSTITUTED PIPERIDINE DERIVATIVES USEFUL AS INHIBITORS OF DIPEPTIDYL PEPTIDASE-1 (DPP-1) - The present invention is directed to 4,4-di-substituted piperidine derivatives, pharmaceutical compositions containing them and their use in the treatment of disorders and conditions modulated by DPP-1. | 09-15-2011 |
20160002219 | IMIDAZOLIN-5-ONE DERIVATIVE USEFUL AS FASN INHIBITORS FOR THE TREATMENT OF CANCER - Disclosed are compounds, compositions and methods for treating various diseases, syndromes, conditions and disorders, including those mediated by inhibition of fatty acid synthase (FASN) enzyme, such as, cancer, obesity or related discorders, and liver related disorders. Such compounds are represented by formula (I) as follows: | 01-07-2016 |