Patent application number | Description | Published |
20140214228 | Graphical User Interface for the Multi-Dimensional Representation of Energy Control - A multi-dimensional energy control system is provided with an energy management software application that organizes the consumption of energy by a device as an n-dimensional energy space, where n is an integer greater than 2, and each axis in the energy space represents an energy consumption characteristic. The energy management application generates instructions for a device in response to calculating a compromise operating point in the energy space. A user interface (UI) connected to the energy management application has a display to receive a graphical representation of the energy space and compromise operating point, and an input to receive user commands for moving the represented compromise operating point in the represented energy space. The energy management application calculates the compromise operating point in the energy space to match the displayed compromise operating point. | 07-31-2014 |
20160036228 | System and Method for Managing AC Power Using Auxiliary DC-to-AC Inversion - A system and method are provided for managing demand for a client with a fluctuating AC power grid demand, using DC-to-AC power inversion as an auxiliary source of power. The inverter has a selectable inversion power output levels connected to the AC client to supply auxiliary power for a portion of the AC power demand. The AC grid demand is averaged. In each of a series of periodic time intervals, a current AC grid demand average in a current time interval is compared to a demand goal, which is the highest AC grid demand average, as measured at an end of a time interval, and selected from a plurality of time intervals. The inverter output power level is selected so that the current AC grid demand average is less than or equal to the demand goal by the end of the current time interval. | 02-04-2016 |
20160036247 | System and Method for Managing Battery Discharge During Critical Peak Pricing Intervals - A system and method are provided for managing battery discharge during critical peak pricing (CPP) intervals. The method provides an alternating current (AC) client with a fluctuating AC grid demand, and a direct current (DC)-to-AC inverter having an input connected to a battery and selectable inversion power output levels connected to the AC client. In response to receiving a CPP warning for a first time interval, a present battery capacity state of charge (SoC) is determined. Also determined is a target peak demand for the AC client over a second time interval that includes the first time interval. The target peak demand defines a desired maximum threshold AC grid demand. In response to determining the present battery capacity SoC and the target peak demand, excess battery capacity is determined, and the excess battery capacity is used to supply auxiliary energy to the AC client during the CPP first time interval. | 02-04-2016 |
Patent application number | Description | Published |
20100047000 | AUTOMATED METHOD AND SYSTEM FOR SELF-CALIBRATION OF IMAGE ON MEDIA SHEETS USING AN AUTO DUPLEX MEDIA PATH - Automated image on media registration and self-calibration using a built-in printing system duplex media path is enabled. The media sheet can be registered in a registration system and a calibration image can be placed on the media sheet after registration of the media. The media sheet can be inverted in the duplex media path and re-fed for detection of calibration image placement accuracy on the media sheet. The registration system can transmit the image registration placement data to a printer controller. Thereafter, the printer controller can adjust system settings to compensate for an image placement registration offset using a calibration algorithm. The invention enables system adjustments without requiring manual measurements or media transfer to an independent scanning device or adding complexity to printing systems. | 02-25-2010 |
20110148957 | Bidirectional Ink Pump - An ink delivery and recovery system includes a first reservoir for containing ink for delivery to a plurality of ink jets of an imaging device, a second reservoir spaced apart from the first reservoir for containing ink for delivery to the first reservoir, and a third reservoir for capturing ink emitted from the plurality of ink jets. A first conduit is connected to the first reservoir and configured to permit flow of ink in a single direction toward the first reservoir. A second conduit is connected to the third reservoir and configured to permit flow of ink in a single direction away from the third reservoir. A third conduit is connected between the second reservoir and the first conduit and second conduit, the third conduit being configured to permit bidirectional flow of ink from the second reservoir toward the first and second conduits and from the first and second conduits toward the second reservoir. A bidirectional pump is associated with the third conduit. | 06-23-2011 |
20110221804 | System And Method For Improving Throughput For Printing Operations In An Indirect Printing System - A printer is configured with a controller that transforms operation of the printer to increase throughput. The printer includes an image receiving member, a printhead configured to eject ink drops onto the image receiving member to form an ink image, a transfix roller configured to move towards and away from the image receiving member to form a transfixing nip with the image receiving member selectively, a release agent applicator configured to engage the image receiving member selectively to apply release agent to the rotatable imaging member, and a controller configured to generate firing signals that operate the printhead from image data and to transform operation of the printer from a first printing process sequence to a second printing process sequence in response to a coverage parameter for image data to be printed being less than a predetermined threshold. | 09-15-2011 |
20120026255 | LIQUID INK DELIVERY SYSTEM INCLUDING A FLOW RESTRICTOR THAT RESISTS AIR BUBBLE FORMATION IN A LIQUID INK RESERVOIR - A fluid ink delivery system includes a receptacle positioned proximate to a plurality of inkjet ejectors, and an ink supply in fluid communication with the receptacle. Ink held in the receptacle may be withdrawn under negative pressure by a pump in the ink supply. A flow restrictor in fluid communication with the pump limits the negative pressure level applied by the pump to be less than a pressure that draws air across a porous member in the receptacle. | 02-02-2012 |
20120044303 | METHOD AND APPARATUS FOR PURGING AND SUPPLYING INK TO AN INKJET PRINTING APPARATUS - An ink delivery system is configured to supply ink to an ink reservoir fluidly coupled to inkjet ejectors and remove ink from a receptacle mounted proximate to the ink reservoir using a single conduit. The ink reservoir is configured to prevent air from being pulled through a reservoir membrane, and a reversible pump is configured to produce positive and negative pressure in the conduit to supply ink to the ink reservoir and remove ink from the receptacle, respectively. | 02-23-2012 |
20120075390 | INK PUMP WITH FLUID AND PARTICULATE RETURN FLOW PATH - A bidirectional sealless ink pumping system used in an inkjet printing device includes a liquid ink reservoir and a pump. The pump moves ink from the reservoir through a pumping chamber to supply ink to printheads in the printer, and moves ink from a recirculation receptacle through the pumping chamber to the reservoir. A portion of the ink in the pumping chamber is drawn out of the pumping chamber to lubricate the moving member and is filtered before returning to the pumping chamber. | 03-29-2012 |
20120098898 | METHOD AND SYSTEM FOR INK DELIVERY AND PURGED INK RECOVERY IN AN INKJET PRINTER - An inkjet printing apparatus is provided with a one-way valve to enable a single conduit to supply ink to an ink reservoir and withdraw purged ink from a receptacle into the ink reservoir. A bi-directional pump is operated in both directions in an alternating manner to withdraw ink from the receptacle when supplying the ink reservoir with ink. | 04-26-2012 |
20120154471 | ALTERNATE IMAGING ORDER FOR IMPROVED DUPLEX THROUGHPUT IN A CONTINUOUS PRINT TRANSFER PRINTER - A method/printer prints images on an “A” side of a first sheet of media and on an “A” side of a second sheet of media in a single full transfer rotation of a drum. The method then prints images on the B side of the first sheet and on an A side of a third sheet in a single full transfer rotation of the drum. Similarly, the method prints images on the B side of the second sheet and on an A side of a fourth sheet in a single full transfer rotation of the drum. This method then prints images on the B side of the third sheet and the B side of the fourth sheet in a single full transfer rotation of the drum. | 06-21-2012 |
20120200636 | WASTE INK RECLAMATION APPARATUS FOR LIQUID INK RECIRCULATION SYSTEM - An ink reclamation receptacle receives ink purged from an inkjet printing apparatus. Ink in the reclamation receptacle wets a porous membrane positioned in the reclamation receptacle, and flows into a flow channel. Negative pressure applied to a port that is placed in fluid communication with the flow channel withdraws ink from the flow channel for use in the inkjet printing apparatus, while ink wetting the pores in the membrane resists a flow of air into the flow channel. | 08-09-2012 |
20120256993 | PRINT PROCESS FOR DUPLEX PRINTING WITH ALTERNATE IMAGING ORDER - A method for performing duplex printing with improved throughput has been developed. The method includes forming an image of a back side of a first duplex page and an image of a front side of a second duplex page on an image receiving member. Two recording media sheets are serially passed through a nip to transfer the image of the first duplex page back side to a bare side of a recording media sheet that also bears the image of the front side of the first duplex page on an obverse side and to transfer the image of the second duplex page to a bare side of a recording media sheet that has not been previously printed. | 10-11-2012 |
20130051900 | Apparatus And Method For Locking And Actuating A Stripper Blade In A Printer - An assembly for actuating a stripper blade in an indirect printer has been developed. The system includes a blade mounted to an elongated member, a first cam, a second cam, and an actuator configured to rotate the first and second cams. The elongated member is fixed in the vertical direction by a channel, and the first cam is configured to limit the horizontal movement of the elongated member. The second cam pivots the elongated member in and out of engagement with an image receiving member when the horizontal movement of the elongated member is constrained. | 02-28-2013 |
20130093135 | SLIDING TANDEM MEDIA FEEDER IN A PRINTER - In a tandem media supply, two vertical stacks of media sheets are stored. The first stack is positioned on a lift plate that rises as top sheets are removed from the stack of media. When the first stack is exhausted, the second stack is moved by an actuator towards a position where the lift plate was loaded with the first stack of media sheets. Movement of the second stack displaces a biased gate to decouple the lift plate from a drive member that elevated the lift plate. The lift plate drops under the effect of gravity to a position where the second stack of media sheets moves onto the lift plate. Once the second stack is on the lift plate, a biasing force returns the biased gate to a position that enables the drive member to elevate the lift plate. | 04-18-2013 |
20130215195 | WASTE INK RECLAMATION APPARATUS FOR LIQUID INK RECIRCULATION SYSTEM - An ink reclamation receptacle receives ink purged from an inkjet printing Apparatus. Ink in the reclamation receptacle wets a porous membrane positioned in the reclamation receptacle, and flows into a flow channel. Negative pressure applied to a port that is placed in fluid communication with the flow channel withdraws ink from the flow channel for use in the inkjet printing apparatus, while ink wetting the pores in the membrane resists a flow of air into the flow channel. | 08-22-2013 |
20140160190 | Print Process For Duplex Printing With Alternate Imaging Order - A method for performing duplex printing with improved throughput has been developed. The method includes forming an image of a back side of a first duplex page and an image of a front side of a second duplex page on an image receiving member. Two recording media sheets are serially passed through a nip to transfer the image of the first duplex page back side to a bare side of a recording media sheet that also bears the image of the front side of the first duplex page on an obverse side and to transfer the image of the second duplex page to a bare side of a recording media sheet that has not been previously printed. | 06-12-2014 |
Patent application number | Description | Published |
20080232250 | SELECTION OF AN AUDIO VISUAL STREAM BY SAMPLING - The embodiments of the present invention provide for methods, devices, and systems for providing quality of service to network data that is received by an intermediate node in a local area network. In some embodiments, network data is categorized based on data flow, and based on such data flow, determining whether such flow exceeds a threshold. If the flow exceeds a threshold, such data flow is accordingly provided quality of service. | 09-25-2008 |
20080291828 | Detection of Signaling Flows - The embodiments of the present invention provide for methods, devices, and systems for providing quality of service (QoS) to network data that is received by an intermediate node in a local area network. In general, the embodiments of the present invention generally evaluate network traffic. Certain streams or flows are copied in appropriate buffer areas and accordingly evaluated by their traffic flow characteristics and further evaluated to determine if such streams/flows contain signaling or control information, which may be based on characteristic key words and/or structures. Based on the signaling or control information extracted, the appropriate stream is accordingly assigned or configured for quality of service (QoS) handling. | 11-27-2008 |
20090217333 | Method and system for discovering vacant DTV channels using DHCP server location - A wireless client device (e.g. a WSD) discovers vacant DTV channels using location information acquired from a Dynamic Host Configuration Protocol (DHCP) server. In one aspect of the invention, a wireless client device discovers vacant DTV channels through direct communication with a local DHCP server and a remote primary user database server. In another aspect of the invention, a wireless client device discovers vacant DTV channels from an access device that communicates with a local DHCP server and a remote primary user database server. | 08-27-2009 |
20100135318 | Enhanced power saving methods and systems for powerline network - Enhanced power saving methods and systems for a powerline network improve power conservation by adaptively regulating the monitoring of a shared carrier sense multiple access (CSMA) region of a beacon period based on current need. The methods and systems include one or more enhanced power saving modes (EPSM). In some embodiments, EPSM include one or both of an enhanced priority resolution (EPR) mode and an enhanced idle sensing (EIS) mode. In some embodiments, an EPSM is selected from a plurality of EPSM in response to an EPSM indicator detected in a beacon region of the beacon period. | 06-03-2010 |
20110313585 | Energy Management System to Reduce the Loss of Excess Energy Generation - Systems and devices for, and methods of, adaptive local energy storage capacity by changing operating set points of regulated energy load devices based on the presence, or absence, of an excess of available, generated energy. | 12-22-2011 |
20120035777 | Offered Actions for Energy Management Based on Anomalous Conditions - Systems and devices for, and methods of, energy management via prompted response options based on detected anomalous conditions. | 02-09-2012 |
20120176076 | Methods and systems for powering auxiliary devices in photovol taic system - Methods and systems for powering auxiliary devices in photovoltaic (PV) systems address shortcomings of conventional PV systems by harvesting unused electricity generated by the PV system to power the auxiliary devices. The methods and systems use PV panel power that is below the PV system inverter's harvesting threshold to charge rechargeable batteries in the auxiliary devices. The invention offers significant advantages over conventional PV systems, including full-time operability of auxiliary devices by virtue of rechargeable batteries that are charged using below threshold PV panel power, reduced field maintenance requirements for auxiliary devices (e.g., battery pack replacement), and elimination of bias in PV system performance data caused by parasitic load of auxiliary devices. | 07-12-2012 |
20120250665 | Method and system for maintaining concurrent membership in multiple networks from a single wireless modem - Method and system for maintaining concurrent membership in multiple networks from a single wireless modem on a wireless networking device. The device time-multiplexes between the networks according to time slots allocated to each network that are shorter than the membership timeout period for the other network. Moreover, whenever the device switches between the networks, the device resets the modem and rejoins the other network using configuration information stored in a nonvolatile memory when the network being rejoined was previously quit. Each network remains unaware of the device's membership in the other network and regards the absence of transmission from the device during the time slot allocated to the other network as a temporary loss of radio contact rather than a membership termination event. The invention enables a single-modem wireless networking device to maintain concurrent ZigBee sessions on a smart energy network and a home automation network. | 10-04-2012 |
20120311317 | Access-controlled customer data offloading to blind public utility-managed device - A method and system for access-controlled customer data offloading uses a blind public utility-managed device. A customer-managed device encrypts collected customer data using per-type, per-period keys and transmits the encrypted customer data to the utility-managed device. The customer-managed device further encrypts the per-type, per-period keys using a master key and transmits the encrypted per-type, per-period keys to the utility-managed device. When the current period ends (e.g., each day at midnight), the customer-managed device generates new per-type, per-period keys and continues the above customer data offloading using the new per-type, per-period keys. As a result, the customer offloads storage of customer data to the public utility without relinquishing control over access to the customer data. Moreover, the fact that the customer data are encrypted by data type and period allows the customer to access and expose the customer data in highly granular fashion. | 12-06-2012 |
20130013119 | Virtual Thermostat System and Method - A virtual thermostat system and method are provided. The method accepts commands via a virtual thermostat interface for establishing temperature set points for a plurality of zones. Energy consumption information is also accepted from a plurality of energy consumption units. Each unit consumes energy at an associated peak power to supply a controlled temperature medium to a corresponding zone. The method also accepts temperature measurements for each zone. Then, consumption commands are sent to each energy consumption unit in response to associated zone temperature set points, while insuring that a combined peak power of the energy consumption units is less than a maximum peak power threshold. In one aspect, the virtual thermostat accepts temperature measurements from a plurality of physical thermostats, each associated with an energy consumption unit. Then, consumption commands are relayed to the energy consumption units via associated physical thermostats. | 01-10-2013 |
20130013124 | System and Method for the Multi-Dimensional Representation of Energy Control - A multi-dimensional energy control system is provided with an energy management software application that organizes the consumption of energy by a device as an n-dimensional energy space, where n is an integer greater than 2, and each axis in the energy space represents an energy consumption characteristic. The energy management application generates instructions for a device in response to calculating a compromise operating point in the energy space. A user interface (UI) connected to the energy management application has a display to receive a graphical representation of the energy space and compromise operating point, and an input to receive user commands for moving the represented compromise operating point in the represented energy space. The energy management application calculates the compromise operating point in the energy space to match the displayed compromise operating point. | 01-10-2013 |
20130211751 | System and Method for Calculating Power Using Contactless Voltage Waveform Shape Sensor - A system and method are provided for calculating power using a voltage waveform shape measurement from a contactless sensor. An electrically conductive medium carries alternating current (AC) electrical current, associated with an AC voltage, from a source node to a destination node. AC current is measured through the electrically conductive medium. Using a contactless sensor, an AC voltage waveform shape is measured. The power usage at the destination node is calculated in response to the AC current measurement, the measurement of the AC voltage waveform shape, and an AC voltage potential. For simplicity, the AC current and AC voltage waveform shape may both be measured at a first node located between the source node and the destination node. The AC voltage potential used in the power usage calculation may be an estimate, an actual measurement, or a value supplied by an external source (e.g., the power utility). | 08-15-2013 |
Patent application number | Description | Published |
20100083018 | FAN SPEED CONTROL OF SILICON BASED DEVICES IN LOW POWER MODE TO REDUCE PLATFORM POWER - In general, in one aspect, the disclosure describes running a cooling fan within a computer at low speed while the computer is in low temperature operations (e.g., idle). The operation of the cooling fan may reduce processor (CPU) temperature enough to decrease processor leakage power, offsetting the power consumption of the fan, and possibly resulting in a net system power reduction. The benefit at the platform level increases further when considering the low efficiency of voltage regulation (VR) in this lower power regime, and potentially reductions in other components (e.g., graphics processor). The optimal fan speed is the speed at which the overall system power is reduced the most (e.g., processor power savings is greater than fan power utilized). The optimal temperature may be determined dynamically during operation or may be determined in manufacturing and applied statically during operation. | 04-01-2010 |
20110154066 | POWER MANAGEMENT SYSTEM AND METHOD - A power manager controls the supply voltage level at a load according to load current demand, and optionally the impedance of the power delivery path, by adjusting the supply voltage. The supply voltage may be reduced by determining a fixed load current that corresponds to a first operating frequency, determining a supply voltage that corresponds to the fixed load current, and then powering the load based on the supply voltage. Alternatively, the supply voltage may be increased along with increasing the operating frequency of the load while maintaining system power consumption within a predetermined limit. | 06-23-2011 |
20120243364 | METHOD AND SYSTEM FOR DYNAMIC POWER MANAGEMENT OF MEMORIES - A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature. | 09-27-2012 |
20120311590 | RESCHEDULING ACTIVE DISPLAY TASKS TO MINIMIZE OVERLAPPING WITH ACTIVE PLATFORM TASKS - In general, in one aspect, a mobile device display includes panel electronics, a backlight driver and a rescheduler. The panel electronics is to generate images on an optical stack of the display based on input from a processing platform of the mobile device. The backlight driver is to control operation of a backlight used to illuminate the optical stack so that the user can see the images generated on the display. The rescheduler is to determine when a timing critical task of the processing platform overlaps with a non-timing critical task of the panel electronics or the backlight driver and reschedule the non-timing critical task until the timing critical task is inactive or a visual tolerance limit has been reached. The rescheduling minimizes overlap between the timing critical tasks and non-timing critical tasks and accordingly reduces power consumption without effecting performance or impacting a user's visual experience. | 12-06-2012 |
20150143147 | FAN CONTROL DURING LOW TEMPERATURE OPERATIONS TO REDUCE PLATFORM POWER - In general, in one aspect, the disclosure describes running a cooling fan within a computer at low speed while the computer is in low temperature operations (e.g., idle). The operation of the cooling fan may reduce CPU temperature enough to decrease CPU leakage power, offsetting the power consumption of the fan, and possibly resulting in a net system power reduction. The benefit at the platform level increases further when considering the low efficiency of voltage regulation (VR) in this lower power regime, and potentially reductions in other components (e.g., graphics processor). The optimal fan speed is the speed at which the overall system power is reduced the most (e.g., CPU power savings is greater than fan power utilized). The optimal temperature may be determined dynamically during-operation or may be determined in manufacturing and applied statically during operation. | 05-21-2015 |
Patent application number | Description | Published |
20090168821 | THERMAL SHUNT FOR ACTIVE DEVICES ON SILICON-ON-INSULATOR WAFERS - An optimized structure for heat dissipation is provided that may include two types of thermal shunts. The first type of thermal shunt employed involves using p and n metal contact layers to conduct heat away from the active region and into the silicon substrate. The second type of thermal shunt involves etching and backfilling a portion of the silicon wafer with poly-silicon to conduct heat to the silicon substrate. | 07-02-2009 |
20090245298 | HYBRID SILICON LASER-QUANTUM WELL INTERMIXING WAFER BONDED INTEGRATION PLATFORM FOR ADVANCED PHOTONIC CIRCUITS WITH ELECTROABSORPTION MODULATORS - Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate. | 10-01-2009 |
20140010253 | HYBRID SILICON LASER-QUANTUM WELL INTERMIXING WAFER BONDED INTEGRATION PLATFORM FOR ADVANCED PHOTONIC CIRCUITS WITH ELECTROABSORPTION MODULATORS - Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate. | 01-09-2014 |
Patent application number | Description | Published |
20090170273 | Dual layer hard mask for block salicide poly resistor (BSR) patterning - In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting. | 07-02-2009 |
20100164001 | Implant process for blocked salicide poly resistor and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include implanting an exposed p type silicon portion of a substrate with a carbon species, wherein endcap regions of a blocked salicide resistor and a p type structure that are both disposed on the exposed p type silicon portion of the substrate are implanted with the carbon species. | 07-01-2010 |
20120161237 | MULTI-GATE TRANSISTORS - Provided are devices having at least three and at least four different types of transistors wherein the transistors are distinguished at least by the thicknesses and or compositions of the gate dielectric regions. Methods for making devices having three and at least four different types of transistors that are distinguished at least by the thicknesses and or compositions of the gate dielectric regions are also provided. | 06-28-2012 |
20130270559 | ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY - Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In sonic embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region. | 10-17-2013 |
20140001569 | HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS | 01-02-2014 |
20140084381 | PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE - Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively. | 03-27-2014 |
20140291737 | TRANSISTOR ARCHITECTURE HAVING EXTENDED RECESSED SPACER AND SOURCE/DRAIN REGIONS AND METHOD OF MAKING SAME - Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (L | 10-02-2014 |
20140308785 | PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE - Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively. | 10-16-2014 |
20140319623 | METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS - Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode. | 10-30-2014 |
20150179525 | HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS - High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers. | 06-25-2015 |
20160035735 | ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY - Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region. | 02-04-2016 |
20160056162 | CMOS-COMPATIBLE POLYCIDE FUSE STRUCTURE AND METHOD OF FABRICATING SAME - CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode. | 02-25-2016 |
20160056293 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER - Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer. | 02-25-2016 |
Patent application number | Description | Published |
20110002841 | Methods of Forming Metal Oxide Nanostructures, and Nanostructures Thereof - A method of forming a metal oxide nanostructure comprises disposing a chelated oligomeric metal oxide precursor on a solvent-soluble template to form a first structure comprising a deformable chelated oligomeric metal oxide precursor layer; setting the deformable chelated oligomeric metal oxide precursor layer to form a second structure comprising a set metal oxide precursor layer; dissolving the solvent-soluble template with a solvent to form a third structure comprising the set metal oxide precursor layer; and thermally treating the third structure to form the metal oxide nanostructure. | 01-06-2011 |
20120222723 | Solar Module Employing Quantum Luminescent Lateral Transfer Concentrator - A solar concentrator module ( | 09-06-2012 |
20130112941 | SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING - Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core. | 05-09-2013 |
20130112942 | COMPOSITE HAVING SEMICONDUCTOR STRUCTURES EMBEDDED IN A MATRIX - Composites having semiconductor structures embedded in a matrix are described. In an example, a composite includes a matrix material. A plurality of semiconductor structures is embedded in the matrix material. Each semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. Each semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates each nanocrystalline shell and anisotropic nanocrystalline core pairing. | 05-09-2013 |
20130206219 | COOPERATIVE PHOTOVOLTAIC NETWORKS AND PHOTOVOLTAIC CELL ADAPTATIONS FOR USE THEREIN - Photovoltaic cells ( | 08-15-2013 |
20130256633 | SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING - Lighting apparatus including a light emitting diode and a plurality of semiconductor structures. Each semiconductor structure includes a quantum dot comprising a nanocrystalline core comprising a first semiconductor material and a nanocrystalline shell comprising a second, different, semiconductor material at least partially surrounding the nanocrystalline core, the quantum dot having a photoluminescence quantum yield (PLQY) of at least 90%. An insulator layer encapsulates the quantum dot. | 10-03-2013 |
20130320298 | SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING - A semiconductor structure comprises a nanocrystalline core of a first semiconductor material, a nanocrystalline shell of a second, different, semiconductor material at least partially surrounding the nanocrystalline core, and an insulator layer encapsulating the nanocrystalline shell and core, wherein an outer surface of the insulator layer is ligand-functionalized. | 12-05-2013 |
20150221838 | COMPOSITE HAVING SEMICONDUCTOR STRUCTURES EMBEDDED IN A MATRIX - Composites having semiconductor structures embedded in a matrix are described. In an example, a composite includes a matrix material. A plurality of semiconductor structures is embedded in the matrix material. Each semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material. Each semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates each nanocrystalline shell and anisotropic nanocrystalline core pairing. | 08-06-2015 |
20150236222 | Semiconductor Structure having Nanocrystalline Core and Nanocrystalline Shell with Insulator Coating - Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core. | 08-20-2015 |
Patent application number | Description | Published |
20150179501 | TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS - Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate. | 06-25-2015 |