Patent application number | Description | Published |
20090072377 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DELAMINATION PREVENTION STRUCTURE - An integrated circuit package system includes: mounting an integrated circuit die over a carrier; attaching a delamination prevention structure over the integrated circuit die; and encapsulating the delamination prevention structure and the integrated circuit die. | 03-19-2009 |
20100038781 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity. | 02-18-2010 |
20110254172 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant. | 10-20-2011 |
20110272807 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity. | 11-10-2011 |
20120326325 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate. | 12-27-2012 |
20130075933 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant. | 03-28-2013 |
Patent application number | Description | Published |
20110103160 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the first memory bank and transfer write data to the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the second memory bank and transfer write data to the second memory bank. The first data read/write unit and the second data read/write unit are located so as to be spaced from each other in the first direction with the memory bank interposed therebetween. | 05-05-2011 |
20110103162 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: a plurality of memory banks disposed at a predetermined distance from each other in a first direction; a common column selection control unit disposed at an outside region of the plurality of memory banks in the first direction, and configured to commonly control access to column areas of the plurality of memory banks; and a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to the corresponding memory cells of the plurality of memory banks. The common column selection control unit generates the column selection signal, and a delay length of the column selection signal is adjusted based on a length of a transmission path of the column selection signal. | 05-05-2011 |
20110103171 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: first and second memory banks located at a predetermined distance from each other; a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to corresponding memory cells in the first and second memory banks; and a column selection signal repeater inserted in the common column selection signal transmission line, and configured to transfer the column selection signal for controlling data access to the memory cell in the first memory bank. A transmission path of the column selection signal for controlling data access to the memory cell in the first memory bank is longer than that of the column selection signal for controlling data access to the memory cell in the second memory bank. | 05-05-2011 |
20120212990 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip. | 08-23-2012 |