| Patent application number | Description | Published |
|---|
| 20080256502 | SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS - An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced. | 10-16-2008 |
| 20090031263 | METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE - Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample. | 01-29-2009 |
| 20090031265 | IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING - A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design. | 01-29-2009 |
| 20090031266 | IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING - A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design. | 01-29-2009 |
| 20090125852 | METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION - In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, the net comprising a plurality of interconnected shapes spanning one or more layers of the integrated circuit, identifying one or more core elements in the graph, the core elements including bridges, articulation points, and biconnected components, computing a first Voronoi diagram for a core portion of the graph on a selected layer, including the core elements, emphasizing regions in the first Voronoi diagram where a critical radius is known, computing a second, higher-order Voronoi diagram in accordance with the emphasized regions, and computing the critical area in accordance with the higher-order Voronoi diagram. | 05-14-2009 |
