Patent application number | Description | Published |
20100188987 | Power learning security in wireless routers - In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area. | 07-29-2010 |
20100329322 | Real-Time Eye Monitor for Statistical Filter Parameter Calibration - In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics. | 12-30-2010 |
20100329325 | Statistically-Adapted Receiver and Transmitter Equalization - In described embodiments, adaptive equalization of a signal in, for example, Serializer/De-serializer transceivers by a) monitoring a data eye in a data path with an eye detector for signal amplitude and/or transition; b) setting the equalizer response of at least one equalizer in the signal path while the signal is present for statistical calibration of the data eye; c) monitoring the data eye and setting the equalizer during periods in which received data is allowed to contain errors (such as link initiation and training periods) and periods in which receive data integrity is to be maintained (such as normal data communication). | 12-30-2010 |
Patent application number | Description | Published |
20090108890 | Internal Supply Voltage Controlled PLL and Methods for Using Such - Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage. | 04-30-2009 |
20100054383 | METHODS AND APPARATUS FOR GENERATING EARLY OR LATE SAMPLING CLOCKS FOR CDR DATA RECOVERY - Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer. | 03-04-2010 |
20100128828 | METHODS AND APPARATUS FOR ADAPTING ONE OR MORE EQUALIZATION PARAMETERS BY REDUCING GROUP DELAY SPREAD - Methods and apparatus are provided for adapting one or more equalization parameters in a communications system by reducing group delay spread. According to one aspect of the invention, one or more equalization parameters in a communications system are adapted by detecting one or more predefined run length patterns in a received signal, such as a plurality of consecutive same-valued bits; evaluating a transition latch value for each of the detected predefined run length patterns, wherein the transition latch value provides an indication of whether the received signal is under-equalized or over-equalized; and adjusting the one or more equalization parameters of the communications system based on the evaluation of the transition latch value. The adjusted equalization parameters may be employed to equalize intersymbol interference. A data eye monitor can be employed to evaluate the transition latch value. | 05-27-2010 |
20100329324 | METHODS AND APPARATUS FOR QUALIFICATION OF UPDATE OF CLOCK RECOVERY AND EQUALIZATION - Methods and apparatus are provided for CDR and equalization update qualification. A block of received data comprising a plurality of multiple tone patterns is processed. Equalization adaptation and/or updates to a timing recovery process can be selectively disabled if one or more of the multiple tone patterns exceed a corresponding predefined threshold. | 12-30-2010 |