Patent application number | Description | Published |
20080307145 | Interconnect and a Method for Designing an Interconnect - A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit. | 12-11-2008 |
20090172414 | DEVICE AND METHOD FOR SECURING SOFTWARE - A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. | 07-02-2009 |
20100030940 | DEVICE AND METHOD FOR SCHEDULING TRANSACTIONS OVER A DEEP PIPELINED COMPONENT - A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit. | 02-04-2010 |
20100169525 | PIPELINED DEVICE AND A METHOD FOR EXECUTING TRANSACTIONS IN A PIPELINED DEVICE - A pipelined device and method for executing transactions in a pipelined device, the method includes: setting limiter thresholds that define a maximal amount of pending transaction requests to be provided from one pipeline stage to another pipeline stage; executing an application while monitoring the performance of a device that comprises pipeline limiters; wherein the executing includes: selectively transferring transaction requests from one stage of the pipeline to another in response to the limiter thresholds, arbitrating between transaction requests at a certain pipeline stage, and executing selected transaction requests provided by the arbitrating. | 07-01-2010 |
20100199010 | DEVICE HAVING PRIORITY UPGRADE MECHANISM CAPABILITIES AND A METHOD FOR UPDATING PRIORITIES - A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests. | 08-05-2010 |
20100325481 | DEVICE HAVING REDUNDANT CORE AND A METHOD FOR PROVIDING CORE REDUNDANCY - A device and a method for providing core redundancy, the device includes: multiple cores; a core operability unit adapted to indicate an operability of each core out of the multiple cores; and a core control signal unit adapted to provide mapping signals that comprise virtual core to physical core mapping signals and physical core to virtual core mapping signals; wherein each core out of the multiple cores comprises at least one interrupt interface, and a crossbar interface which are responsive to at least one mapping signal. | 12-23-2010 |
20150146612 | METHOD AND SYSTEM FOR PROCESSING DATA FLOWS - The method and system supports multiple bandwidth traffic over a single CPRI (common public radio interface) link ( | 05-28-2015 |
20150146613 | METHOD AND APPARATUS FOR RESETTING AT LEAST ONE NODE WITHIN A CPRI RADIO BASE STATION SYSTEM - A method of resetting at least one node within a Common Public Radio Interface (CPRI) radio base station system is described. The method comprises, at an end-point Radio Equipment Controller (REC) node within the CPRI radio base station system, receiving on a slave port a reset notification, and in response thereto transmitting on the slave port a reset notification comprising a reset bit being set within at least ten hyperframes. | 05-28-2015 |