| Patent application number | Description | Published |
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| 20090004981 | HIGH EFFICIENCY DIGITAL TRANSMITTER INCORPORATING SWITCHING POWER SUPPLY AND LINEAR POWER AMPLIFIER - A novel apparatus and method of improving the power efficiency of a digital transmitter for non-constant-amplitude modulation schemes. The power efficiency improvement mechanism of the invention leverages the high efficiency of a switched-mode power supply (SMPS) that supplies the high DC current to the transmitter's power amplifier, while compensating for its limitations using predistortion. The predistortion may be achieved using any suitable technique such as digital signal processing, hardware techniques, etc. A switched mode power supply (i.e. switching regulator) is used to provide a slow form (i.e. reduced bandwidth) of envelope tracking (based on a narrower bandwidth distorted version of the envelope waveform) such that the switching regulator can use a lower switching rate corresponding to the lower bandwidth, thereby obtaining high efficiency in the switching regulator. The resulting AM-AM and AM-PM distortions in the power amplifier are compensated through predistortion of the digital amplitude modulating signal which dictates the envelope at the PA input. Similarly, the phase modulation is also compensated prior to the PA, such that once it undergoes the distortion in the PA, the end result is sufficiently close to the desired phase. | 01-01-2009 |
| 20090257396 | System and method of adaptive frequency hopping with look ahead interference prediction - A novel and useful adaptive frequency hopping scheme for wireless devices and networks operating in a congested environment of similar devices, where capacity maximization is desired. The hopping sequence of each wireless link is dynamically adapted such that the impact of the surrounding interference is minimized and the interference induced onto the coexisting systems is also minimized. The scheme detects the repetitive presence of interference on a particular channel and comprises a replacement mechanism for swapping the interfered frequency-channel with one that would be clear for that particular time-slot. The mechanism detects interference during a redundant portion of the transmission (i.e. header or trailer) without having to experience packet failures (i.e. data loss). If the interference impact (e.g. corrupted header bits) exceeds a predefined threshold, that frequency channel is declared temporarily unusable for that time slot and is replaced with another in accordance with a frequency replacement policy. Periodic interference at a particular frequency, originating from a coexisting system of similar operating parameters, may also be detected at instances that are distant from the timeslots for which that particular frequency is to be used, such that frequency replacement in the hopping sequence can be scheduled ahead of time and collisions would be avoided altogether. | 10-15-2009 |
| 20100008338 | HIGH TRANSMISSION POWER USING SHARED BLUETOOTH AND WIRELESS LOCAL AREA NETWORK FRONT END MODULE - A novel and useful system for providing high transmission power using a shared Bluetooth and Wireless Local Area Network (WLAN) front end module (FEM). A single power amplifier in the front end module is shared between the WLAN and Bluetooth radio cores, thus providing a high power transmission option (Bluetooth class 1) for the Bluetooth core. Interface circuitry in the FEM couple either the WLAN TX output or the Bluetooth TX output to the input of the power amplifier and couple the output of the power amplifier to the external antenna. In the receive direction, the interface circuitry steers the antenna input to the respective WLAN or Bluetooth receivers in accordance with one or more control signals. Alternatively, a switch in the WLAN/Bluetooth radio chip functions to switch the Bluetooth TX output to a conventional FEM, thereby allowing the FEM power amplifier to be shared between the WLAN and Bluetooth radio cores. | 01-14-2010 |
| 20120082008 | Low Power Radio Controlled Clock Incorporating Independent Timing Corrections - A timekeeping device that tracks the time provided by a digital broadcast and the protocol of that broadcast, defined by its data frame structure and modulation scheme, are adapted to allow for superior performance of the timekeeping devices in terms of range of operation, immunity to interference, ability to operate with lower cost antennas due to enhanced link robustness, and reduced energy consumption. The timekeeping device operates with infrequent receptions of the broadcast by relying on independent self-compensation. This alleviates the need for frequent receptions to ensure timing accuracy while reducing energy consumption. The mean and variability of successive measurements of timing drift are evaluated and an estimated upper bound for the drift-estimation error is set. Based on this bound, the device employs a reception strategy that relies on less frequent receptions, corresponding to the error in estimating the drift rather than to the magnitude of the drift itself | 04-05-2012 |
| 20120093204 | PROCESSOR, MODEM AND METHOD FOR CANCELLING ALIEN NOISE IN COORDINATED DIGITAL SUBSCRIBER LINES - A method of cancelling alien noise in coordinated DSL lines, a method of smoothing an alien noise covariance estimate, and a processor and modem for cancelling alien noise in coordinated DSL lines. In one embodiment, the method of cancelling alien noise includes: (1) estimating alien noise vectors for at least some training symbols, (2) arranging the alien noise vectors in a matrix dimensioned for a number of coordinated DSL lines, (3) orthonormally transforming the matrix into a lower-triangular matrix and (4) computing alien noise prediction filters from the lower-triangular matrix. | 04-19-2012 |
| 20120169397 | Mixed Signal Integrator Incorporating Extended Integration Duration - A mixed-signal integrator, having an analog input and a digital output, is adapted to perform an integration operation partially in the analog domain and partially in the digital domain while eliminating the limitations of a conventional analog integrator. The integrator also digitizes a signal of interest without the use of a conventional sampling operation followed by a conventional analog-to-digital converter. The analog integrator portion generates an analog integration signal limited between low and high rail voltages defined by two comparators with corresponding threshold voltages. When either rail voltage is reached, the polarity of the input signal is reversed to prevent the integration result from exceeding that rail. Each such event is also tracked in digital logic, which provides a count whenever two consecutive such events correspond to the two different rails. At the end of the integration duration this count serves as the digital representation of the integration result. | 07-05-2012 |
| 20120244824 | MINIMIZATION OF RMS PHASE ERROR IN A PHASE LOCKED LOOP BY DITHERING OF A FREQUENCY REFERENCE - A novel and useful apparatus for and method of minimizing the phase distortions experienced at the output of a phase locked loop (PLL) by dithering of its input frequency reference to overcome additive interference that is parasitically suffered on it. The frequency reference signal is dithered in a controlled manner using either indirect or direct coupling. The dither signal may be a single clock or is generated by switching between two or more of the existing clock signals generated, or may be produced by a dedicated pseudo-random noise generator having specific spectral properties. In indirect coupling, the dither signal is coupled through a bond wire sufficiently close in proximity to the frequency reference circuit input. This dominates the jitter inflicted onto the frequency reference signal and upconverts its spectral content to higher frequency, thus eliminating the more damaging low-frequency jitter caused by the interfering RF signal. In direct coupling, the dither signal is coupled to the reference frequency input using a network of components directly connected thereto. | 09-27-2012 |
| 20120252382 | PREDISTORTION CALIBRATION AND BUILT IN SELF TESTING OF A RADIO FREQUENCY POWER AMPLIFIER USING SUBHARMONIC MIXING - A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog/RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times. | 10-04-2012 |
