Patent application number | Description | Published |
20080279007 | BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING - Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed. | 11-13-2008 |
20080279008 | NON-VOLATILE STORAGE WITH BOOSTING USING CHANNEL ISOLATION SWITCHING - Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed. | 11-13-2008 |
20090296475 | VERIFICATION PROCESS FOR NON-VOLATILE STORAGE - When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements. | 12-03-2009 |
20110026331 | PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY - Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage. | 02-03-2011 |
20110235423 | VERIFICATION PROCESS FOR NON-VOLATILE STORAGE - When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements. | 09-29-2011 |
20110255345 | PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS - A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells. | 10-20-2011 |
20130223155 | TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE - A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation. | 08-29-2013 |
20140036601 | TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE - A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation. | 02-06-2014 |
Patent application number | Description | Published |
20080302963 | SHEET BEAM-TYPE TESTING APPARATUS - An electron beam apparatus such as a sheet beam based testing apparatus has an electron-optical system for irradiating an object under testing with a primary electron beam from an electron beam source, and projecting an image of a secondary electron beam emitted by the irradiation of the primary electron beam, and a detector for detecting the secondary electron beam image projected by the electron-optical system; specifically, the electron beam apparatus comprises beam generating means | 12-11-2008 |
20080308729 | Apparatus for inspection with electron beam, method for operating same, and method for manufacturing semiconductor device using former - A substrate inspection apparatus | 12-18-2008 |
20090032708 | Inspection system by charged particle beam and method of manufacturing devices using the system - An inspection apparatus by an electron beam comprises: an electron-optical device | 02-05-2009 |
20090039262 | ELECTRON BEAM APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE APPARATUS - The present invention provides an electron beam apparatus for irradiating a sample with primary electron beams to detect secondary electron beams generated from a surface of the sample by the irradiation for evaluating the sample surface. In the electron beam apparatus, an electron gun has a cathode for emitting primary electron beams. The cathode includes a plurality of emitters for emitting primary electron beams, arranged apart from one another on a circle centered at an optical axis of a primary electro-optical system. The plurality of emitters are arranged such that when the plurality of emitters are projected onto a straight line parallel with a direction in which the primary electron beams are scanned, resulting points on the straight line are spaced at equal intervals. | 02-12-2009 |
20090050822 | Electron beam apparatus and method of manufacturing semiconductor device using the apparatus - The present invention provides an electron beam apparatus for evaluating a sample surface, which has a primary electro-optical system for irradiating a sample with a primary electron beam, a detecting system, and a secondary electro-optical system for directing secondary electron beams emitted from the sample surface by the irradiation of the primary electron beam to the detecting system. | 02-26-2009 |
20110104830 | APPARATUS FOR INSPECTION WITH ELECTRON BEAM, METHOD FOR OPERATING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING FORMER - A substrate inspection apparatus | 05-05-2011 |
20120032079 | INSPECTION SYSTEM BY CHARGED PARTICLE BEAM AND METHOD OF MANUFACTURING DEVICES USING THE SYSTEM - An inspection apparatus by an electron beam comprises: an electron-optical device | 02-09-2012 |
20140034831 | INSPECTION SYSTEM BY CHARGED PARTICLE BEAM AND METHOD OF MANUFACTURING DEVICES USING THE SYSTEM - An inspection apparatus by an electron beam comprises: an electron-optical device | 02-06-2014 |