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Ootsuka, Hyogo

Hiroyuki Ootsuka, Hyogo JP

Patent application numberDescriptionPublished
20090195947PROTECTIVE CIRCUIT - A protective circuit connected between a terminal of a semiconductor integrated circuit and ground (GND), comprises: a first diode having an anode connected to the terminal of the semiconductor integrated circuit; a second diode having an anode connected to GND and a cathode connected to the cathode of the first diode; a transistor having a collector or drain connected to the terminal of the semiconductor integrated circuit, and an emitter or source connected to GND; and at least one third diode connected in series in a forward direction from the cathode of the first diode toward the base or gate of the transistor.08-06-2009

Takeshi Ootsuka, Hyogo JP

Patent application numberDescriptionPublished
20100017541MEMORY DEVICE AND MEMORY DEVICE CONTROLLING APPARATUS - A memory device controlling apparatus of the present invention includes a device information requesting part that requests device information with respect to a memory device, when recognizing that the memory device is connected to the memory device controlling apparatus, and an extension activating part that activates an extension of the memory device based on the device information acquired in the device information requesting part. The memory device controlling apparatus accesses the memory device using the extension in the memory device. Such a configuration enables the memory device and the memory device controlling apparatus to be operated in an optimum operation mode in accordance with the characteristics of each bus, a host PC, and the memory device.01-21-2010
20100077280SEMICONDUCTOR RECORDING DEVICE - The present invention intends to provide a semiconductor recording device that is able to continuously record data and has high reliability even in a case where writing errors frequently occur. When data to be written is recorded as an error correction code (ECC) in a plurality of physical blocks constituting a nonvolatile memory and a writing error occurred, a time interval between the writing error that occurred immediately before and the present writing error is detected. Then, when the time interval is within a first reference time, an error position management unit registers a writing error occurrence block number and block numbers grouped with the writing error occurrence block in the ECC. Then, the writing error registered in the error position management unit is read at a predetermined timing, and the error is corrected on the basis of the ECC and the corrected data is rewritten. In this manner, since overflow of a buffer memory of the host apparatus can be avoided, real-time recording can be realized even in the case where the writing errors frequently occurred.03-25-2010
20100138593MEMORY CONTROLLER, SEMICONDUCTOR RECORDING DEVICE, AND METHOD FOR NOTIFYING THE NUMBER OF TIMES OF REWRITING - User data transferred from a host apparatus and a first information table 06-03-2010
20100153629SEMICONDUCTOR MEMORY DEVICE - A command analyzer 06-17-2010
20100174951SEMICONDUCTOR MEMORY DEVICE, HOST DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A host device 07-08-2010
20100293322SEMICONDUCTOR RECORDING APPARATUS AND SEMICONDUCTOR RECORDING SYSTEM - A semiconductor recording apparatus includes a logical-to-physical conversion table 11-18-2010
20110041036SEMICONDUCTOR RECORDING DEVICE - An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface 02-17-2011

Patent applications by Takeshi Ootsuka, Hyogo JP