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Ooka, JP
Fumihiko Ooka, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090072381 | SEMICONDUCTOR DEVICE WITH DOUBLE-SIDED ELECTRODE STRUCTURE AND ITS MANUFACTURING METHOD - According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring. | 03-19-2009 |
| 20110089551 | SEMICONDUCTOR DEVICE WITH DOUBLE-SIDED ELECTRODE STRUCTURE AND ITS MANUFACTURING METHOD - According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring. | 04-21-2011 |
Hideyuki Ooka, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20100123253 | SEMICONDUCTOR DEVICE - An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively. | 05-20-2010 |
| 20110260218 | SEMICONDUCTOR DEVICE - An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively. | 10-27-2011 |
Hiroshi Ooka, Kiryu-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090250942 | ENGINE STARTER - An electromagnetic controller includes an exciting coil unit that is provided with a coil main body and an exciting piece that is positioned at a tip end side of the coil main body so as to be magnetized according to an excitation of the coil main body; and a plunger that is disposed in a ring-shaped space formed at an inner diameter side of the exciting coil unit so as to be movable in the ring-shaped space in an axial center direction, the plunger being displaceable from a non-acting position to an acting position at a tip end side under an attracting force based on magnetization of the exciting piece, wherein an urging member is provided at the inner diameter side of the exciting coil unit so as to urge the plunger to a side of the non-acting position according to demagnetization of the exciting piece. | 10-08-2009 |
Hiroshi Ooka, Gunma JP
| Patent application number | Description | Published |
|---|---|---|
| 20100013334 | Starter - In a starter having a motor comprising a rear bracket | 01-21-2010 |
Junji Ooka, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20120103401 | SOLAR CELL PANEL - A solar cell panel that is capable of preventing damage to the edge portions of the panel. The solar cell panel is provided with a pair of first protective ribs ( | 05-03-2012 |
Kenji Ooka, Hekinan-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20080264319 | Embroidery data processor, sewing machine, and computer readable medium for embroidery data processing - An embroidery data processor includes an embroidery data storage that stores embroidery data for sewing embroidery patterns by an embroiderable sewing machine; an embroidery data preparator that prepares the embroidery data of the embroidery patterns to be sewn by reading the embroidery data from the embroidery data storage or by receiving the embroidery data from external source; and a data generator that generates temporary stitch data for temporarily sewing an interlining on an underside of a workpiece cloth prior to embroidery sewing based on the embroidery data prepared by the embroidery data preparator. | 10-30-2008 |
Kentaro Ooka, Ota-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110309476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device including a protection diode for preventing electrostatic breakdown employing a low capacitance protection diode, an occupation area of a Zener diode as a voltage limiting element is not needed on a front surface of a semiconductor substrate. A P+ type embedded diffusion layer is formed in a P+ type semiconductor substrate. This is then covered by a non-doped first epitaxial layer. A high resistivity N type second epitaxial layer is then formed on the first epitaxial layer. The second epitaxial layer is divided by a P+ isolation layer into a first protection diode forming region and a second protection diode forming region. An N+ type embedded layer extending from the front surface of the first epitaxial layer of the first protection diode forming region to the first epitaxial layer and the second epitaxial layer, and so on are then formed. A Zener diode is formed by a P+ type upward diffusion layer extending from the P+ type embedded diffusion layer and the N+ type embedded layer. | 12-22-2011 |
Masakazu Ooka, Naka-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090282885 | Method of forming spring washer blind-holes into a piston for an automobile transmission - The problem to be solved by the present invention is to clear up an eccentric load onto a pin and a problem of deformation and cavity due to flowing material during extrusion when spring washer blind-holes in a piston for an automobile transmission is formed by extrusion with a pin. After an annular region along the peripheral edge portion on the back of an end plate | 11-19-2009 |
Susumu Ooka, Gunma JP
| Patent application number | Description | Published |
|---|---|---|
| 20110293945 | VINYLIDENE FLUORIDE RESIN FILM - Provided is a vinylidene fluoride resin film that has good adhesiveness to a base material, achieves good dispersivity even when a pigment is contained in large amounts, and has excellent thermal stability during a forming process. | 12-01-2011 |
Yasunobu Ooka, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100084102 | PAPERMAKING ADDITIVE AND FILLED PAPER - To effectively impart sizing performance to paper, while reducing the amounts of an internal sizing agent and aluminum sulfate, the invention provides as a papermaking additive a mixture of a cationic copolymer having a hydrophobic group whose quarterization ratio is 40% by mole or more, or an amphoteric copolymer having a hydrophobic group which has the same quarterization ratio as above, and in which the ratio of the anion equivalent to the cation equivalent is 0.1 to 90%, and a filler (a pretreated filler). The pretreated filler is one in which suitable water repellency is imparted to the filler. Hence, by adding this to pulp slurry, followed by a wet papermaking, the pretreated filler is efficiently adsorbed onto pulp fibers having anionic property, so that effective sizing performance can be imparted to the paper by using a smaller amount thereof than the internal sizing agent, while reducing the amounts of the internal sizing agent and the aluminum sulfate. | 04-08-2010 |