| Patent application number | Description | Published |
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| 20090006657 | Enabling consecutive command message transmission to different devices - In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed. | 01-01-2009 |
| 20090006670 | Cache for a host controller - In one embodiment, the present invention includes a host controller having a cache memory to store entries each including, at least, a command header (CH) portion having data associated with a command from the host controller to one of multiple devices coupled to a port multiplier, and a physical region descriptor (PRD) portion to store address information associated with a next address for data transfer with regard to the command. Other embodiments are described and claimed. | 01-01-2009 |
| 20090327773 | SERIAL ATA (SATA) POWER OPTIMIZATION THROUGH AUTOMATIC DEEPER POWER STATE TRANSITION - A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial low power state without first transitioning to the Active state. The transition from the Partial state to the Slumber state is direct and the transition may be enabled, but not negotiated through a handshaking process. | 12-31-2009 |
| 20100067133 | COMMAND SUSPENSION IN RESPONSE, AT LEAST IN PART, TO DETECTED ACCELERATION AND/OR ORIENTATION CHANGE - In an embodiment, an apparatus is provided that may include circuitry to, in response at least in part to detected change in at least one of acceleration and orientation of storage, request suspension of at least one command currently stored in at least one pending command queue that is intended for execution, at least in part, by the storage. The at least one command having been previously issued by the circuitry but being currently unexecuted, at least in part, by the storage. The circuitry also being to store, in response at least in part to the detected change, at least one copy of the at least one command for later re-issuance by the circuitry, and to request replacement of at least one command in the at least one queue with at least one other command to park at least one head of the storage. | 03-18-2010 |
| Patent application number | Description | Published |
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| 20080237310 | Die backside wire bond technology for single or stacked die package - Methods and apparatus to provide die backside connections are described. In one embodiment, the backside of a die is metallized and coupled to another die or a substrate. Other embodiments are also described. | 10-02-2008 |
| 20080315421 | Die backside metallization and surface activated bonding for stacked die packages - Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described. | 12-25-2008 |
| 20090019196 | Quality of Service (QoS) Processing of Data Packets - The present disclosure provides a method for providing Quality of Service (QoS) processing of a plurality of data packets stored in a first memory. The method may include determining a queue of a plurality of queues causing an interrupt using contents of an interrupt status register, the queue comprising address of at least one data packet of the plurality of data packets. The method may further include performing a logical operation between the contents of the interrupt status register and an interrupt mask of a plurality of interrupt masks, the plurality of interrupt masks stored in a second memory. The method may also include processing the plurality of data packets based on the logical operation and incrementing an interrupt mask address pointer stored in a third memory, thereby pointing to another interrupt mask of the plurality of interrupt masks. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 01-15-2009 |
| 20090065951 | STACKED DIE PACKAGE - The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed. | 03-12-2009 |
| 20100169750 | FIRMWARE VERIFICATION USING SYSTEM MEMORY ERROR CHECK LOGIC - Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values. | 07-01-2010 |
| 20120003792 | STACKED DIE PACKAGE - The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed. | 01-05-2012 |
