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Ontalus, US
Viorel Ontalus, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110027956 | Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure - A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device. | 02-03-2011 |
| 20110095343 | BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT - A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions. | 04-28-2011 |
| 20110101506 | Stress Memorization Technique Using Silicon Spacer - A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process. | 05-05-2011 |
Viorel Ontalus, Danbury, CT US
| Patent application number | Description | Published |
|---|---|---|
| 20090148988 | METHOD OF REDUCING EMBEDDED SIGE LOSS IN SEMICONDUCTOR DEVICE MANUFACTURING - Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET. | 06-11-2009 |
| 20100006952 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME - An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region of and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type. | 01-14-2010 |
Viorel C. Ontalus, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110062525 | METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR - A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc. | 03-17-2011 |
Viorel C. Ontalus, Fishkill, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110049582 | ASYMMETRIC SOURCE AND DRAIN STRESSOR REGIONS - A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region. | 03-03-2011 |
Viorel C. Ontalus, Danbury, CT US
| Patent application number | Description | Published |
|---|---|---|
| 20090146223 | PROCESS AND METHOD TO LOWER CONTACT RESISTANCE - A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface. | 06-11-2009 |
| 20100240227 | ACTIVATING DOPANTS USING MULTIPLE CONSECUTIVE MILLISECOND-RANGE ANNEALS - A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds. | 09-23-2010 |