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Onouchi
Hisanari Onouchi, Aichi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090030227 | Polyisocyanide Derivative Having Controlled Helical Main Chain Structure - The object is to provide: a method for producing a polymer having a stable right-handed or left-handed helical structure from a single type of monomer in a per-selective manner and controlling the proportion between a polymer having the right-handed helical structure and a polymer having the left-handed helical structure; and a polymeric material which can be used for the formation of any of the right-handed and left-handed helical structures. Thus, disclosed are: a method for production of a polyisocyanide derivative having a stable helical main chain structure with a right-handed or left-handed helix or a mixture thereof from a single type of monomer by polymerizing an aromatic isocyanate having a substituent harboring a structure —CONH in the aromatic ring and a hydrophobic moiety having 6 or more carbon atoms in a polymerization solvent, wherein the direction of the helix depends on the polarity of the polymerization solvent; a poly(aromatic isocyanide) derivative produced by the method; and an aromatic isocyanide which is useful as a monomer for use in the production of the poly(aromatic isocyanide) derivative. | 01-29-2009 |
Hisanari Onouchi, Osaka JP
| Patent application number | Description | Published |
|---|---|---|
| 20110163268 | POLARIZING FILM - The present invention provides a polarizing film containing an azo compound represented by the following formula (1): | 07-07-2011 |
Masafumi Onouchi, Higashimurayama JP
| Patent application number | Description | Published |
|---|---|---|
| 20100117697 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR CLOCK SIGNAL SYNCHRONIZATION - There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed. | 05-13-2010 |
Masafumi Onouchi, Tachikawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20100083011 | INFORMATION PROCESSING DEVICE - In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like. | 04-01-2010 |
Masafumi Onouchi, Hachioji JP
| Patent application number | Description | Published |
|---|---|---|
| 20080235519 | Data processing method and data processing device - An object is to achieve improvement in efficiency in a case where encoding processing of data and encryption processing are executed in parallel with each other. A program of a first accelerator core out of multiple accelerator cores is reconfigured for encryption processing in order to perform encryption processing on encoded data. At this time, control is extended so that the time required for encoding processing of data for one frame and the total time of the program rewrite time for the first accelerator core and the time which the first accelerator core requires for implementing encryption processing of accumulated encoded data will be nearly equal to each other. The control is performed by a first general-purpose processor out of multiple general-purpose processors. By minimizing a wasted time during which hardware does not execute any arithmetic and logic operation, improvement in efficiency in a case where encoding processing of data and encryption processing are executed in parallel with each other is achieved. | 09-25-2008 |
Tatsuya Onouchi, Aichi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100179790 | Method for Forming Functional Spectral Filter - To provide a functional spectral filter through which, it is possible for an observer wearing the functional spectral filter to change his or her color sensitivity (ease of color distinction), and which is for designing a color scheme easy to be distinguished for a color deficient observer by using the filter. A functional spectral filter including a multilayer is formed in accordance with a thin film design (an optimization method) determined by use of a color vision theory so as to make color sensitivity into a desired pattern. With respect to combinations that two colors among a plurality of specified colors are combined, color differences in the respective combinations are made close to a color difference given in advance. Alternatively, with respect to specified combinations, the color differences are made small or the color differences are made large. | 07-15-2010 |