Patent application number | Description | Published |
20090040849 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized. | 02-12-2009 |
20090040850 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced. | 02-12-2009 |
20090040851 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily. | 02-12-2009 |
20100110818 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation. | 05-06-2010 |
Patent application number | Description | Published |
20100091654 | Method For Controlling Path Switching In Wireless Communication System, And Controller And Wireless Base Station In That System - In a wireless communication system including a wireless terminal, a plurality of wireless base stations that wirelessly communicate with the wireless terminal, and a controller that changes the path used for communication with the wireless terminal from a first path via a first wireless base station to a second path via a second wireless base station, the controller monitors the amount of remaining data to the wireless terminal at the first wireless base station, controls to the timing to change to the second path according to the monitor result. | 04-15-2010 |
20120236827 | MOBILE COMMUNICATION SYSTEM, BASE STATION, AND HANDOVER EXECUTION METHOD - A mobile communication system includes a plurality of base stations, an upper node, and a mobile station. In this mobile communication system, while a first base station that is currently connected via radio to the mobile station is receiving a first downlink signal from a second base station that was previously connected via radio to the mobile station and that received the first downlink signal from the upper node for transmission to the mobile station, when the mobile station is connected via radio to a third base station as a result of a handover, the first base station sends a redirection request signal requesting the second base station to redirect the first downlink signal to the third base station. Then, in response to the redirection request signal, the second base station redirects the first downlink signal to the third base station. | 09-20-2012 |
Patent application number | Description | Published |
20130246842 | INFORMATION PROCESSING APPARATUS, PROGRAM, AND DATA ALLOCATION METHOD - In an information processing apparatus, a first selecting unit selects, as a source stripe, a stripe in which at least one of blocks stores a data item and another one of the blocks stores an error-correcting code for the data item, among a plurality of stripes each including a group of storage areas of a plurality of blocks that are located one on each of a plurality of storage devices. A second selecting unit selects, as a destination stripe, a stripe in which at least one of blocks stores a data item and in which the number of available blocks is equal to or greater than the number of blocks of the source stripe which store data items, among the stripes other than the source stripe. A moving unit moves the data item stored in the source stripe to the available block of the destination stripe. | 09-19-2013 |
20140201175 | STORAGE APPARATUS AND DATA COMPRESSION METHOD - A storage apparatus includes a data storage unit, management information storage unit, compression judgment unit, and compression control unit. The data storage unit stores the data of files. The management information storage unit stores management information on the files. The compression judgment unit evaluates compression effectiveness for a file at prescribed execution timing and determines whether the compression of the file is appropriate or not. The compression control unit updates the management information so as to reflect the determination result obtained by the compression judgment unit, and then stores the compressed data of the file in a compressed format in the data storage unit if the determination result indicates that the compression is appropriate, and stores the uncompressed data of the file in an uncompressed format in the data storage unit if the determination result indicates the compression is inappropriate. | 07-17-2014 |
20150100822 | STORAGE CONTROL APPARATUS AND COMPUTER READABLE STORAGE MEDIUM - A storage control apparatus forms a RAID by plural storage media and stores and holds data on a file-by-file basis. A number-of-writable-times management unit manages the number of writable times for each storage medium. A write-destination management unit manages data write destinations in the storage media. When updating write object data whose write destination is one of storage media constituting a group (first storage medium), a relocation unit relocates the write object data by setting a write destination to a second storage medium which is different from the first storage medium. A write-destination update unit updates the data write destinations in the storage media managed by the write-destination management unit according to the relocating. Through the relocating, the storage control apparatus is able to control the number of writable times which decreases along with data writing. | 04-09-2015 |