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Oh, Ichon-Shi
Ic Su Oh, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20100064163 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal. | 03-11-2010 |
| 20100090736 | DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled. | 04-15-2010 |
Jae-Geun Oh, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090061602 | METHOD FOR DOPING POLYSILICON AND METHOD FOR FABRICATING A DUAL POLY GATE USING THE SAME - A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced. | 03-05-2009 |
Sang Mook Oh, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20110291681 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a first power line coupled to a first power transfer pad; a second power line coupled to a second power transfer pad; and a test option unit coupled to the first and second power lines and configured to couple the first and second power lines. | 12-01-2011 |
Sang-Rok Oh, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20080213990 | METHOD FOR FORMING GATE ELECTRODE IN SEMICONDUCTOR DEVICE - A method for forming a gate electrode in a semiconductor device includes providing a substrate, forming a gate insulation layer over the substrate, forming first and second conductive layers over the gate insulation layer, forming a hard mask pattern over the second conductive layer, etching the second conductive layer using the hard mask pattern as an etch mask, performing an oxidation process to form an anti-oxidation layer on a sidewall of the etched second conductive layer, and etching the first conductive layer using the hard mask as an etch mask. | 09-04-2008 |
| 20080227281 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE - A method for fabricating a semiconductor device includes forming a sacrificial layer having a stack structure of a first insulation layer, a first conductive layer and a second insulation layer over a substrate, forming a recess by etching the sacrificial layer and the substrate, forming a gate insulation layer over a recess surface, filling a second conductive layer in the recess and between etched sacrificial layers, forming a gate electrode metal layer, a gate hard mask layer and a gate mask pattern over a resultant substrate, etching layers formed below the gate mask pattern by using the gate mask pattern until the first conductive layer is exposed, thereby forming an initial gate pattern, forming a capping layer on a sidewall and a top portion of the initial gate pattern, and etching an exposed portion by using the capping layer as a mask until the first insulation layer is exposed, thereby forming a final gate pattern. | 09-18-2008 |
| 20090130841 | METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE - A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask. | 05-21-2009 |
| 20090163010 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer is formed, forming an interlayer dielectric layer to fill gap between the gate patterns, and etching the interlayer dielectric layer between the gate patterns to form a contact hole. | 06-25-2009 |
Sang-Won Oh, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090039402 | SEMICONDUCTOR DEVICE WITH ASYMMETRIC TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line. | 02-12-2009 |
Young-Hwan Oh, Ichon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090040805 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation. | 02-12-2009 |