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Offen, IL
Daniel Offen, Kfar Haroe IL
| Patent application number | Description | Published |
|---|---|---|
| 20090010895 | Isolated cells and populations comprising same for the treatment of CNS diseases - An isolated human cell and populations thereof is provided comprising at least one astrocytic phenotype and at least one mesenchymal stem cell phenotype, wherein the mesenchymal stem cell phenotype is not an astrocytic phenotype. | 01-08-2009 |
| 20090257987 | Method of generating dopamine-secreting cells - Methods of generating cells which secrete dopamine are disclosed. One method comprises incubating mesenchymal stem cells in a culture medium comprising brain derived neurotrophic factor (BDNF), wherein the culture medium comprises no more than 0.1 μM retinoic acid (RA). Another method comprises incubating mesenchymal stem cells in a culture medium comprising glial-derived neurotrophic factor GDNF, transforming growth factor β3 (TGFβ3) and retinoic acid (RA). Cells generated by the above-described methods are also disclosed as well as uses thereof. | 10-15-2009 |
| 20100021434 | Isolated Oligodendrocyte-Like Cells and Populations Comprising Same for the Treatment of CNS Diseases - Isolated human cells and populations thereof are provided comprising at least one oligodendrocyte phenotype and at least one mesenchymal stem cell phenotype, wherein the mesenchymal stem cell phenotype is not an oligodendrocyte phenotype. Methods of generating and using same are also provided. | 01-28-2010 |
| 20100093600 | REGULATION OF NEUROTRANSMITTERS SEQUESTRATION AND RELEASE THROUGH MANIPULATION OF THE VESICULAR FUNCTIONS - A method of selecting an agent comprising a neuroprotecting activity is disclosed. The method comprises: | 04-15-2010 |
Zeev Offen, Haifa IL
| Patent application number | Description | Published |
|---|---|---|
| 20090172284 | METHOD AND APPARATUS FOR MONITOR AND MWAIT IN A DISTRIBUTED CACHE ARCHITECTURE - A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle. | 07-02-2009 |
| 20090248983 | TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS - A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device. | 10-01-2009 |
| 20100235320 | ENSURING COHERENCE BETWEEN GRAPHICS AND DISPLAY DOMAINS - A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device. | 09-16-2010 |
Zeev Offen, Folsom IL
| Patent application number | Description | Published |
|---|---|---|
| 20100161907 | POSTING WEAKLY ORDERED TRANSACTIONS - A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system. | 06-24-2010 |