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Odanaka
Junko Odanaka, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090041799 | Physiologically Active Substance NK13650P3, Method of Producing the Same and Use Thereof - A physiologically active substance NK13650P3 having the following physicochemical properties or a pharmacologically acceptable salt thereof. 1) Appearance: pale yellow powder 2) Molecular formula: C | 02-12-2009 |
Satoshi Odanaka, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20080285224 | INFORMATION PROCESSING APPARATUS - An information processing apparatus having improved cooling efficiency is disclosed. The information processing apparatus includes a first chassis and a second chassis separated from each other at a prescribed distance, the first chassis accommodating a substrate on which high heat generating parts such as a CPU and a chipset are mounted, and the second chassis accommodating low heat generating and low heat resistance parts. Because of this structure, the first chassis and the second chassis are thermally isolated, and the surface area of the apparatus is increased, thereby improving the cooling efficiency of the apparatus. | 11-20-2008 |
| 20080285229 | HEAT DISSIPATING MEMBER, HEAT DISSIPATING MECHANISM, AND INFORMATION PROCESSING APPARATUS - A heat dissipating member, a heat dissipating mechanism, and an information processing apparatus capable of improving the cooling efficiency without increasing the size of the apparatus are disclosed. In the information processing apparatus, it becomes possible to effectively transfer heat from a unit such as a memory disposed in an inner space of the apparatus to the outside regardless of the layout position of the unit by using the heat dissipating mechanism fixed to a unit and a heat dissipation surface so that the heat is transferred from the unit to the heat dissipation surface. | 11-20-2008 |
Shigeru Odanaka, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090055784 | METHOD FOR VERIFYING SAFETY APPARATUS AND SAFETY APPARATUS VERIFIED BY THE SAME - A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device. | 02-26-2009 |
| 20090164955 | METHOD FOR VERIFYING SAFETY APPARATUS AND SAFETY APPARATUS VERIFIED BY THE SAME - A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device. | 06-25-2009 |
Shinji Odanaka, Osaka JP
| Patent application number | Description | Published |
|---|---|---|
| 20090019419 | Method for forming LSI pattern - First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed. | 01-15-2009 |