Obeng, US
Edward Kwabena Obeng, Niskayuna (schenectady), NY US
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20100063927 | METHOD AND SYSTEM FOR CLEARING FINANCIAL INSTRUMENTS - A method and system for electronically clearing financial instruments through a clearing system in which a per item cost of clearing instruments varies with the time of day. The method may include the steps of receiving electronic files of items containing data scanned from financial instruments including an amount of each instrument, applying a rule to sort the items by determining, for each of the associated financial instruments, whether the item be stored or forwarded for clearing the instrument without storage. The rule may include a step of determining whether an amount of the instrument exceeds a predetermined value, and if the amount of the instrument exceeds the predetermined value, forwarding the instrument for clearing without storage. If the amount of the instrument does not exceed the first predetermined value, the associated rule may cause the system to store the item representing the instrument for forwarding at a later time when the per item fee for clearing is lower. The threshold amount may vary depending upon the per item fee charged at the time the item is received by the system, in a case where the per item fee charged changes over the course of a business day, and different time intervals may have different threshold amounts. The system may include a control system for receiving the associated electronic files from a scanning device and have a processor programmed to apply a rule to sort the files by determining, for each of the instruments, whether the associated electronic file should be stored or forwarded for clearing, a gateway server for receiving the associated electronic files from the scanning devices and transmitting the files to the control system, and an image export server for receiving the associated electronic files from the control system, converting the files to a preferred format, storing the files in storage, retrieving the files from storage for clearing and transmitting the files to the Federal Reserve for clearing. | 03-11-2010 |
20120136791 | METHOD AND SYSTEM FOR CLEARING FINANCIAL INSTRUMENTS - A method and system for electronically clearing financial instruments through a clearing system in which a per item cost of clearing instruments varies with the time of day. Files of items containing data scanned from financial instruments including an amount of each instrument may be received by a control system that may apply a rule to sort the items by determining whether the item be stored or forwarded for clearing. The rule may include a step of determining whether an amount of the instrument exceeds a predetermined value or meets a certain criteria, and if so, forwarding the instrument for clearing without storage. If the amount of the instrument does not exceed the first predetermined value or meet the criteria, the system may store the item for forwarding at a later time when the per item fee for clearing is lower. | 05-31-2012 |
Rebecca C. Obeng, Cambridge, MA US
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20130259883 | CLASS I MHC PHOSPHOPEPTIDES FOR CANCER IMMUNOTHERAPY AND DIAGNOSIS - A set of phosphorylated peptides are presented by HLA A*0101, A*0201, A*0301, B*4402, B*2705, B*1402, and B*0702 on the surface of melanoma cells. They have the potential to (a) stimulate an immune response to the cancer, (b) to function as immunotherapeutics in adoptive T-cell therapy or as a vaccine, (c) to facilitate antibody recognition of the tumor boundaries in surgical pathology samples, and (d) act as biomarkers for early detection of the disease. Phosphorylated peptides are also presented for other cancers. | 10-03-2013 |
Rebecca C. Obeng, Charlottesville, VA US
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20150224182 | TARGET PEPTIDES FOR IMMUNOTHERAPY AND DIAGNOSTICS - A set of target peptides are presented by HLA A*0101, A*0201, A*0301, B*4402, B*2705, B*1402, and B*0702 on the surface of disease cells. They are envisioned to among other things (a) stimulate an immune response to the proliferative disease, e.g., cancer, (b) to function as immunotherapeutics in adoptive T cell therapy or as a vaccine, (c) facilitate antibody recognition of tumor boundaries in surgical pathology samples, (d) act as biomarkers for early detection and/or diagnosis of the disease, and (e) act as targets in the generation antibody-like molecules which recognize the target-peptide/MHC complex. | 08-13-2015 |
Yaw S. Obeng, Frisco, TX US
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20080230846 | METHOD OF MANUFACTURING METAL SILICIDE CONTACTS - A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts. | 09-25-2008 |
20080315322 | METHOD FOR RELIABLY REMOVING EXCESS METAL DURING METAL SILICIDE FORMATION - A method for manufacturing a semiconductor device. The method comprises forming a metal layer on a silicon-containing layer located on a semiconductor substrate. The method also comprises reacting a portion of the metal layer with the silicon-containing layer to form a metal silicide layer. The method further comprises removing an unreacted portion of the metal layer on the metal silicide layer by a removal process. The removal process includes delivering a flow of an acidic solution to a surface of the unreacted portion of the metal layer, wherein the acidic solution delivered to the surface is substantially gas-free. | 12-25-2008 |
20090020791 | PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT ETCH-STOP LINER LAYERS - Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer stack can include multiple buffer layers formed between a first type stress layer (e.g., a tensile stress layer) and a second type stress layer (e.g., a compressive stress layer) during the CMOS fabrication. Specifically, the buffer layer stack can be formed after the etching process of the first type stress layer but prior to the etching process of the second type stress layer, and thus to protect the etched first type stress layer during the subsequent etching process of the overlaid second type stress layer. In addition, a portion of the buffer layer stack can be formed between, for example, the compressive stress layer and the underlying PMOS device to enhance their adhesion. | 01-22-2009 |
20100041231 | FUSI Integration Method Using SOG as a Sacrificial Planarization Layer - A method for making a transistor | 02-18-2010 |
Yaw S. Obeng, Frederick, MD US
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20150363682 | AUTHENTICATION ARTICLE AND PROCESS FOR MAKING SAME - An authentication article includes: a substrate including: a first surface; a second surface disposed laterally to the first surface and at a depth below the first surface; and a plurality of indentations including the depth at the second surface of the substrate; and an array disposed on the substrate and including a plurality of analytes, the analytes being disposed in the indentations at a depth below a first surface of the substrate and provided to emit an authentication signature in response to being subjected to a probe stimulus. A process for authenticating the authentication article includes: providing the authentication article; subjecting the analytes to a probe stimulus; acquiring a response from the plurality of analytes in response to being subjected to the probe stimulus; and determining whether the response is the authentication signature to authenticate the, wherein the authentication article is not authenticated if the response is not the authentication signature for the array. | 12-17-2015 |
Yaw Samuel Obeng, Vienna, VA US
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20090069790 | SURFACE PROPERTIES OF POLYMERIC MATERIALS WITH NANOSCALE FUNCTIONAL COATING - A method of manufacturing a polymeric object that comprises providing a polymeric substrate, and exposing said substrate to a first stage that includes an initial plasma reactant so as to reduce a water contact angle of a surface of the substrate, and, wherein the initial plasma treatment activates the surface to a grafting reaction, The method further includes exposing the activated substrate surface to a second stage that includes a second plasma reactant to thereby deposit a grafted material on the activated substrate surface to form a grafted surface. | 03-12-2009 |
Yaw Samuel Obeng, Frisco, TX US
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20110097884 | METHOD TO ATTAIN LOW DEFECTIVITY FULLY SILICIDED GATES - A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes. | 04-28-2011 |
Yaw Samuel Obeng, Frederick, MD US
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20150103504 | SURFACE PROPERTIES OF POLYMERIC MATERIALS WITH NANOSCALE FUNCTIONAL COATING - An electronic device comprising a substrate having a component-side surface and a moisture protection film covering the component-side surface. The moisture protection film includes a first water layer bonded to component-side surface that is an activated surface, wherein the activated surface has a lower water contact angle than the substrate surface before the surface activation. The film includes a first graphed layer of a plasma-reacted first set of precursor molecules graphed to the first water layer, wherein the first water layer forms a first bonding link between the substrate surface and the reacted first set precursor molecules. The film includes a second water layer bonded to the first graphed layer. The film includes a second graphed layer of a plasma-reacted second set of precursor molecules graphed to the second water layer, wherein the second water layer forms a second bonding link between the second water layer and the reacted second set of precursor molecules. | 04-16-2015 |
Yew S. Obeng, Frisco, TX US
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20090111224 | FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER - A method for making a transistor | 04-30-2009 |