Patent application number | Description | Published |
20080202258 | MEMS SHOCK SENSORS - A shock sensor comprises a substrate and at least one flexure coupled to the substrate and configured to deflect upon an application of force to the shock sensor sufficient to deflect the flexure. Deflection of the at least one flexure produces a detectable change in an electrical property of the shock sensor. Examples of detectable changes in an electrical property of the shock sensor include an open circuit condition, a closed circuit condition, and a variation in voltage of a piezo-electric detector. In some embodiments, the change in the electrical property of the shock sensor may be remotely read by interrogation of a radio frequency identification transponder positioned on the substrate using a remote radio frequency identification transceiver. The disclosure also relates to a shock sensing system and method of shock detection. | 08-28-2008 |
20080299904 | WIRELESS COMMUNICATION SYSTEM - A wireless communication system comprises a first communication module including a transmitter configured to generate a modulated magnetic field and a second communication module including a receiver. The receiver of the second communication module includes a solid magnetic field sensor configured to sense the magnetic field. Information is transferred from the first communication module to the second communication module via the magnetic field. | 12-04-2008 |
20090002883 | Wire-assisted magnetic write device with phase shifted current - A magnetic device includes a write element having a write element tip and a conductive coil for carrying a current to induce a first field from the write element. A conductor proximate the write element tip carries the current to generate a second field that augments the first field. A driver provides the current to the conductive coil and the conductor, and a circuit phase shifts the current through the conductor relative to the current through the conductive coil. | 01-01-2009 |
20090237837 | MAGNETIC RECORDING HEAD - A method of fabricating a recording head includes depositing an insulator material onto at least a portion of a first member, wherein the insulator material forms an insulator film having a film thickness. The method further includes depositing a writer pole material onto the insulator film, wherein the writer pole material forms a writer pole member, and wherein the insulator film is between the writer pole member and a contact layer. Further, in some embodiments, the film thickness determines the distance between the writer pole member and the first contact member and also determines the distance between the writer pole member and the second contact member. | 09-24-2009 |
20090251827 | Recording head for reducing side track erasure - The present invention relates to a head having an air bearing surface for confronting the surface of a storage medium. The head includes a first pole that is spaced apart from a second pole. At least one non-magnetic spacer is positioned between the first pole and the second pole such that the first pole is magnetically decoupled from the second pole. In a further aspect, one or both of the first pole and the second pole can be elliptical in shape. | 10-08-2009 |
20100021767 | DISCRETE TRACK MEDIA - A method of fabricating a discrete track magnetic recording media. A base layer is provided onto which repeating and alternating magnetic layer and non-magnetic layers are deposited. The thickness of the magnetic layer corresponds to the width of the track of the recording media. A cylindrical rod can be used as the base layer, such that the alternating magnetic and non-magnetic layers spiraling or concentric layers around the rod. The resulting media layer can be cut or sliced into individual magnetic media or used to imprint other media discs with the discrete pattern of the media layer. | 01-28-2010 |
20100102308 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH OXIDE LAYER - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode. | 04-29-2010 |
20100104115 | MICRO MAGNETIC SPEAKER DEVICE WITH BALANCED MEMBRANE - A micro magnetic device with a micro magnetic speaker unit having a first element, a second element, and a membrane therebetween. Each of the elements comprises a body, a pole of soft magnetic material, an electrically conductive coil positioned around the pole, and a permanent magnet connected to the membrane. The first element and the second element are magnetically identical. A plurality of speaker units can be combined to provide a speaker array. | 04-29-2010 |
20100110764 | PROGRAMMABLE METALLIZATION CELL SWITCH AND MEMORY UNITS CONTAINING THE SAME - An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel. | 05-06-2010 |
20100110765 | Non-Volatile Memory Cell with Programmable Unipolar Switching Element - A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element. | 05-06-2010 |
20100193761 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH LAYERED SOLID ELECTROLYTE STRUCTURE - Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed. | 08-05-2010 |
20100219156 | THREE-DIMENSIONAL MAGNETIC STRUCTURE FOR MICROASSEMBLY - Micro structures and methods for creating complex, 3-dimensional magnetic micro components and their application for batch-level microassembly. Included is a method for making complex, 3-dimensional magnetic structures by depositing a first photoimageable magnet/polymer material on a substrate and patterning to form at least one first active magnetic area and at least one first sacrificial area, then depositing a second photoimageable magnet/polymer material and patterning to form at least one second active magnetic area and at least one second sacrificial area, and then removing the first sacrificial area and the second sacrificial area. Also included is a micro structure self assembly method, the method including providing a substrate having at least one magnetic receptor site, and engaging a 3-dimensional magnetic micro structure having a magnetic micro component with the substrate by aligning the magnetic micro component with the magnetic receptor site. | 09-02-2010 |
20110002161 | PHASE CHANGE MEMORY CELL WITH SELECTING ELEMENT - A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array. | 01-06-2011 |
20110006276 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 01-13-2011 |
20110007545 | Non-Volatile Memory Cell Stack with Dual Resistive Elements - A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element. | 01-13-2011 |
20110007546 | Anti-Parallel Diode Structure and Method of Fabrication - An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region. | 01-13-2011 |
20110122678 | Anti-Parallel Diode Structure and Method of Fabrication - An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region. | 05-26-2011 |
20110228599 | Non-Volatile Memory Cell with Programmable Unipolar Switching Element - A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element. | 09-22-2011 |
20120032131 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH OXIDE LAYER - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode. | 02-09-2012 |
20120040496 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH OXIDE LAYER - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode. | 02-16-2012 |
20120087186 | MULTI-BIT MEMORY WITH SELECTABLE MAGNETIC LAYER - An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity. In response to magnetic saturation of the first selection layer, programming of a logical state to the second storage layer is allowed. | 04-12-2012 |
20120127786 | FLUX PROGRAMMED MULTI-BIT MAGNETIC MEMORY - An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed. | 05-24-2012 |
20120149183 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 06-14-2012 |
20120199936 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 08-09-2012 |
20120224418 | MULTI-BIT MEMORY WITH SELECTABLE MAGNETIC LAYER - An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity. In response to magnetic saturation of the first selection layer, programming of a logical state to the second storage layer is allowed. | 09-06-2012 |
20130003225 | MAGNETIC RECORDING HEAD - A method of fabricating a recording head includes depositing an insulator material onto at least a portion of a first member, wherein the insulator material forms an insulator film having a film thickness. The method further includes depositing a writer pole material onto the insulator film, wherein the writer pole material forms a writer pole member, and wherein the insulator film is between the writer pole member and a contact layer. Further, in some embodiments, the film thickness determines the distance between the writer pole member and the first contact member and also determines the distance between the writer pole member and the second contact member. | 01-03-2013 |
20130017413 | Discrete Track Media - A method of fabricating a discrete track magnetic recording media. A base layer is provided onto which repeating and alternating magnetic layer and non-magnetic layers are deposited. The thickness of the magnetic layer corresponds to the width of the track of the recording media. A cylindrical rod can be used as the base layer, such that the alternating magnetic and non-magnetic layers spiraling or concentric layers around the rod. The resulting media layer can be cut or sliced into individual magnetic media or used to imprint other media discs with the discrete pattern of the media layer. | 01-17-2013 |
20130330901 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH LAYERED SOLID ELECTROLYTE STRUCTURE - Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed. | 12-12-2013 |