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Nouri
Abdallah Nouri, Brampton CA
| Patent application number | Description | Published |
|---|---|---|
| 20120067540 | DIRECTIONAL SOLIDIFICATION SYSTEM AND METHOD - The present invention relates to an apparatus and method for purifying materials using a rapid directional solidification. Devices and methods shown provide control over a temperature gradient and cooling rate during directional solidification, which results in a material of higher purity. The apparatus and methods of the present invention can be used to make silicon material for use in solar applications such as solar cells. | 03-22-2012 |
Ali Nouri, Washington, DC US
| Patent application number | Description | Published |
|---|---|---|
| 20100292102 | System and Method For Preventing Synthesis of Dangerous Biological Sequences - A system and method for prohibiting synthesis of dangerous biological sequences are provided. The system includes a synthesizer for synthesizing biological sequences, a computer system in communication with the synthesizer, and a database including at least one prohibited biological sequence for which synthesis is prohibited. The system receives a requested biological sequence for which synthesis is desired, and compares the requested biological sequence to the database. The system prohibits synthesis of the requested biological sequence by the synthesizer if the requested biological sequence matches at least one prohibited biological sequence in the database, and allows synthesis of the requested biological sequence by the synthesizer if no match is found in the database. The computer system could form part of the synthesizer, and the requested biological sequence could be input by a user using a control panel of the synthesizer. A centralized security server is also provided for central monitoring and control of synthesis by one or more remote synthesizers, and a security chip is provided for securing individual synthesizers. | 11-18-2010 |
Arnaud Nouri, Kogenheim FR
| Patent application number | Description | Published |
|---|---|---|
| 20080210127 | PREFABRICATED MEMBRANE BASED ON MODIFIED POLYURETHANE BITUMINOUS BINDER AND PROCESS FOR PRODUCTION - The present invention has for its object a prefabricated sealing membrane formed by a support, coated on at least one surface, and preferably impregnated throughout, with a modified bitumen base composition, characterized in that the thermoplastic bituminous composition for coating and/or impregnation is a bituminous binder modified by a thermoplastic polyurethane having the following weight proportion: | 09-04-2008 |
Dana W. Nouri, Mclean, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20090020454 | Reduced elevation catalyst return line for a fluid catalytic cracking unit - The present invention is an improved regenerated catalyst bend assembly for a fluid catalytic cracking unit. In a preferred embodiment, the reduced elevation (“RE-bend” or “REL-bend”) regenerated catalyst return line assembly of the present invention has an outlet elevation that is lower than the inlet elevation of the RE-bend or REL-bend regenerated catalyst return line assembly, and a process for utilizing the assembly in a fluid catalytic cracking unit. The present invention is especially useful in the modification of existing fluid catalytic cracking units to lower the elevation of the outlet of the regenerated catalyst return line assembly, thereby providing needed space to increase the fluid catalytic cracking reactor riser length. | 01-22-2009 |
Faran Nouri, Las Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110278651 | NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME - NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer. | 11-17-2011 |
Faran Nouri, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080280413 | METHODS FOR FORMING A TRANSISTOR - Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity. | 11-13-2008 |
| 20080299735 | METHODS FOR FORMING A TRANSISTOR - Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity. | 12-04-2008 |
| 20100264470 | NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME - NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer. | 10-21-2010 |
Pouneh Nouri, Washington, DC US
| Patent application number | Description | Published |
|---|---|---|
| 20100081689 | Methods and Compositions for the Treatment of Iron Toxicity - Methods and compositions for the treatment of iron toxicity using nitroxides, particularly 4-hydroxy-2,2,6,6-tetramethyl- | 04-01-2010 |