| Patent application number | Description | Published |
|---|
| 20110145559 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED STEADY STATE DEADLINES - A method of dynamically controlling a central processing unit is disclosed. The method may include determining when a CPU enters a steady state, calculating an optimal frequency for the CPU when the CPU enters a steady state, guaranteeing a steady state CPU utilization, and guaranteeing a steady state CPU utilization deadline. | 06-16-2011 |
| 20110145617 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES - A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget. | 06-16-2011 |
| 20110145824 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH REDUCED FREQUENCY OSCILLATIONS - A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle. | 06-16-2011 |
| 20110173474 | DYNAMIC LOW POWER MODE IMPLEMENTATION FOR COMPUTING DEVICES - The aspects enable a computing device or microprocessor to determine a low power mode that provides the most system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Aspects provide a mechanism for determining an optimal low power configuration made up of a set of low power modes for the various resources within the computing device by determining which low power modes are valid at the time the processor enters an idle state, ranking the valid low power modes by expected power savings given the current device conditions, determining which valid low power mode provides the greatest power savings while meeting the latency requirements, and selecting a particular low power mode for each resource to enter. | 07-14-2011 |
| 20110173475 | DOMAIN SPECIFIC LANGUAGE, COMPILER AND JIT FOR DYNAMIC POWER MANAGEMENT - The aspects enable a computing device or microprocessor to determine a low-power mode that maximizes system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. The various aspects provide mechanisms and methods for compiling a plurality of low power resource modes to generate one or more synthetic low power resources from which can be selected an optimal low-power mode configuration made up of a set of selected synthetic low power resources. | 07-14-2011 |
| Patent application number | Description | Published |
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| 20110173463 | SYSTEM AND METHOD OF TUNING A DYNAMIC CLOCK AND VOLTAGE SWITCHING ALGORITHM BASED ON WORKLOAD REQUESTS - A method of tuning a dynamic clock and voltage switching algorithm is disclosed and may include setting a default responsivity, determining whether a workload is registering after the workload is added, assigning a unique identifier to the workload if the workload is registering, and receiving a required responsivity from the workload. | 07-14-2011 |
| 20110173471 | SYSTEM AND METHOD OF SAMPLING DATA WITHIN A CENTRAL PROCESSING UNIT - A method of sampling data within a central processing unit (CPU) is disclosed. The method may include monitoring CPU activity, determining whether the CPU enters idle, and executing a dynamic clock and voltage switching (DCVS) algorithm if the CPU enters idle. | 07-14-2011 |
| 20110173617 | SYSTEM AND METHOD OF DYNAMICALLY CONTROLLING A PROCESSOR - A method of executing a dynamic clock and voltage scaling (DCVS) algorithm in a central processing unit (CPU) is disclosed and may include monitoring CPU activity and determining whether a workload is designated as a special workload when the workload is added to the CPU activity. | 07-14-2011 |
| 20110173628 | SYSTEM AND METHOD OF CONTROLLING POWER IN AN ELECTRONIC DEVICE - A method of utilizing a node power architecture (NPA) system, the method includes receiving a request to create a client, determining whether a resource is compatible with the request, and returning a client handle when the resource is compatible with the request. | 07-14-2011 |
