| Patent application number | Description | Published |
|---|
| 20090097851 | OPTICAL INTERCONNECT SYSTEM PROVIDING COMMUNICATION BETWEEN COMPUTER SYSTEM COMPONENTS - An optical interconnect system for communication between computer system components is described. The system includes an optical data communication path and a plurality of optical taps, each optical tap optically coupling a respective computer system component to the optical data communication path. Each optical tap splits power from an optical signal received from the data communication path or from a light source generating a data signal from its associated computer component resulting in another optical signal. Each optical tap splits light in accordance with a respective power ratio relationship between reflectivity and transmissivity. The ratio relationships of the optical taps together provide a predetermined communication reliability metric for signals traversing the optical interconnect system between computer system components. | 04-16-2009 |
| 20090103345 | Three-dimensional memory module architectures - Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer. | 04-23-2009 |
| 20090103854 | Photonic interconnects for computer system devices - Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect comprises a plurality of on-chip waveguides. Additionally, the photonic interconnect may include a plurality of off-chip waveguides, and at least one optoelectronic converter. The at least one optoelectronic converter can be photonically coupled to a portion of the plurality of on-chip waveguides, can be photonically coupled to a portion of the plurality of off-chip waveguides, and is in electronic communication with at least one computer system component. | 04-23-2009 |
| 20090240890 | PROGRAM THREAD SYNCRONIZATION - A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized. | 09-24-2009 |
| 20090274413 | Photonic interconnects for computer system devices - Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect comprises a plurality of on-chip waveguides. Additionally, the photonic interconnect may include a plurality of off-chip waveguides, and at least one optoelectronic converter. The at least one optoelectronic converter can be photonically coupled to a portion of the plurality of on-chip waveguides, can be photonically coupled to a portion of the plurality of off-chip waveguides, and is in electronic communication with at least one computer system component. | 11-05-2009 |
| 20100023692 | MODULAR THREE-DIMENSIONAL CHIP MULTIPROCESSOR - A chip multiprocessor die supports optional stacking of additional dies. The chip multiprocessor includes a plurality of processor cores, a memory controller, and stacked cache interface circuitry. The stacked cache interface circuitry is configured to attempt to retrieve data from a stacked cache die if the stacked cache die is present but not if the stacked cache die is absent. In one implementation, the chip multiprocessor die includes a first set of connection pads for electrically connecting to a die package and a second set of connection pads for communicatively connecting to the stacked cache die if the stacked cache die is present. Other embodiments, aspects and features are also disclosed. | 01-28-2010 |
| 20100194470 | Integrated Circuit Package - An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die. | 08-05-2010 |
| 20100332764 | Modular Three-Dimensional Chip Multiprocessor - A chip multiprocessor die supports optional stacking of additional dies. The chip multiprocessor includes a plurality of processor cores, a memory controller, and stacked cache interface circuitry. The stacked cache interface circuitry is configured to attempt to retrieve data from a stacked cache die if the stacked cache die is present but not if the stacked cache die is absent. In one implementation, the chip multiprocessor die includes a first set of connection pads for electrically connecting to a die package and a second set of connection pads for communicatively connecting to the stacked cache die if the stacked cache die is present. Other embodiments, aspects and features are also disclosed. | 12-30-2010 |
| 20110113208 | STORING CHECKPOINT DATA IN NON-VOLATILE MEMORY - Methods and systems for storing checkpoint data in non-volatile memory are described. According to one embodiment, a data storage method includes executing an application using processing circuitry and during the execution, writing data generated by the execution of the application to volatile memory. An indication of a checkpoint is provided after writing the data. After the indication has been provided, the method includes copying the data from the volatile memory to non-volatile memory and, after the copying, continuing the execution of the application. The method may include suspending execution of the application. According to another embodiment, a data storage method includes receiving an indication of a checkpoint associated with execution of one or more applications and, responsive to the receipt, initiating copying of data resulting from execution of the one or more applications from volatile memory to non-volatile memory. In some embodiments, the non-volatile memory may be solid-state non-volatile memory. | 05-12-2011 |
| 20110119525 | CHECKPOINTING IN MASSIVELY PARALLEL PROCESSING - One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory. | 05-19-2011 |
