| Patent application number | Description | Published |
|---|
| 20080238494 | METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION - The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L | 10-02-2008 |
| 20090002015 | ERROR CORRECTING LOGIC SYSTEM - The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system. | 01-01-2009 |
| 20090010043 | Configurable SRAM System and Method - A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently. | 01-08-2009 |
| 20090055826 | Multicore Processor Having Storage for Core-Specific Operational Data - An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data processing system, where the method includes providing a multicore processor that contains a plurality of processor cores and a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency for each of the plurality of processor cores. The method further includes operating a scheduler coupled to an operating system and to the multicore processor, where the scheduler is operated to be responsive at least in part to information read from the memory to schedule the execution of threads to individual ones of the processor cores for a more optimal usage of energy. | 02-26-2009 |
| 20090141536 | Structure for a Configurable SRAM System and Method - A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently. | 06-04-2009 |
| 20090144677 | Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices - A design structure for a circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The design structure for the circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors. | 06-04-2009 |
| 20090172615 | METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION - The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L | 07-02-2009 |
| 20090217059 | Utilizing Networked Three Dimensional Voltage Regulation Modules (VRM) to Optimize Power and Performance of a Device - A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event. | 08-27-2009 |
| 20100011278 | Soft Error Correction in Sleeping Processors - An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence. | 01-14-2010 |
