Noriaki Maeda
Noriaki Maeda, Tachikawa JP
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20100177580 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD THEREOF - Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers. | 07-15-2010 |
20110063895 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM - A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line. | 03-17-2011 |
Noriaki Maeda, Chuo-Ku JP
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20110003757 | PHARMACEUTICAL COMPOSITIONS FOR TREATING FATTY LIVER DISEASE - The present invention provides a pharmaceutical composition useful as a therapeutic agent for fatty liver disease. A pharmaceutical composition, which comprises (1S)-1,5-anhydro-1-[5-(azulen-2-ylmethyl)-2-hydroxyphenyl]-D-glucitol or a pharmaceutically acceptable salt thereof, (1S)-1,5-anhydro-1-[3-(1-benzothiophen-2-ylmethyl)-4-fluorophenyl]-D-glucitol or a pharmaceutically acceptable salt thereof, or alternatively, (1S)-1,5-anhydro-1-[4-chloro-3-(4-ethoxybenzyl)phenyl]-D-glucitol or a pharmaceutically acceptable salt thereof, more specifically such a pharmaceutical composition for treating fatty liver disease, such as nonalcoholic fatty liver disease in one embodiment, or nonalcoholic simple fatty liver and/or nonalcoholic steatohepatitis in another embodiment. | 01-06-2011 |
Noriaki Maeda, Higashiyamato JP
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20090116279 | Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 05-07-2009 |
20100188887 | Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 07-29-2010 |
20120044775 | Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 02-23-2012 |
20130272058 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 10-17-2013 |
Noriaki Maeda, Fussa JP
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20080247258 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced. | 10-09-2008 |
Noriaki Maeda, Fujisawa-Shi JP
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20130264850 | RECLINING APPARATUS - A reclining apparatus includes: a base plate; a ratchet plate including a recessed portion having a inner circumferential surface provided with internal teeth; a pole including an outer circumferential surface of the pole provided with external teeth engageable with the internal teeth; and a guide, which is provided in the base plate to guide the pole between a locked position and an unlocked position, wherein the pole includes: a first cut external teeth part having a first tooth surface, in which a first side receiving a forward load is cut; and a second cut external teeth part having a second tooth surface, in which a second side receiving the rearward load is cut, and wherein a cutting degree of the first cut external teeth part is different from a cutting degree of the second cut external teeth part. | 10-10-2013 |
Noriaki Maeda, Kawasaki-Shi JP
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20150102421 | Semiconductor Device - A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions. | 04-16-2015 |