Patent application number | Description | Published |
20090174695 | SCANNING LINE DRIVING CIRCUIT FOR ACTIVE MATRIX AND IMAGE DISPLAY DEVICE - A first contact hole formed in a gate driving circuit is covered with an electrically conductive oxide film formed to be connected to the first contact hole and having a first pattern. The periphery of the electrically conductive oxide film is surrounded by an electrically conductive oxide film (a sacrifice electrode) formed simultaneously with the electrically conductive oxide film and having a second pattern form. | 07-09-2009 |
20100060602 | TOUCH SCREEN, TOUCH PANEL AND DISPLAY DEVICE - Each detection column wiring is constituted by a set of a first metal wiring having a zigzag pattern and a second metal wiring having a structure axisymmetric with the first metal wiring about a column direction as an axis, wherein the first metal wiring is constituted by first sloped portions which are obliquely sloped by an inclination angle of 45 degrees with respect to the column direction, and first parallel portions which are parallel with the column direction and are continuous with the first sloped portions, such that the first sloped portions and the first parallel portions are repeatedly placed in a zigzag shape along the column direction. Each detection row wiring also has the same structure. A sloped portion out of the first sloped portions of the first metal wiring is always orthogonally and spatially intersected, at its middle point, with a sloped portion out of the second sloped portions of the third metal wiring at its middle point. There is also the same orthogonal relationship among the other portions. | 03-11-2010 |
20100289992 | LIQUID CRYSTAL DISPLAY DEVICE - Provided is a liquid crystal display device including contact hole parts in a gate line driving circuit, and light shielding layers formed of a metal material on a color filter substrate, where an insulating film is formed so as to cover the light shielding layer of the color filter substrate in a region on the array substrate, the area being opposed to the contact hole parts. | 11-18-2010 |
20110142191 | SHIFT REGISTER CIRCUIT - A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit. | 06-16-2011 |
20120207266 | SHIFT REGISTER CIRCUIT - A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit. | 08-16-2012 |
20120293457 | TOUCH SCREEN, TOUCH PANEL AND DISPLAY DEVICE - A detection column wiring includes a set of a first metal wiring having a zigzag pattern and a second metal wiring having a structure axisymmetric with the first metal wiring about a column direction. The first metal wiring includes first sloped portions obliquely sloped by an inclination angle of 45° with respect to the column direction, and first parallel portions parallel with the column direction and continuous with the first sloped portions; the first sloped portions and the first parallel portions being repeatedly placed in a zigzag shape along the column direction. Each detection row wiring has the same structure. A sloped portion of the first sloped portions of the first metal wiring is always orthogonally and spatially intersected, at its middle point, with a sloped portion of the second sloped portions of the third metal wiring at its middle point. Other portions have the same orthogonal relationship. | 11-22-2012 |
20130140568 | IMAGE DETECTOR - An image detector comprises: an active matrix-type TFT array substrate having a pixel area, in which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, a data line, and a bias line; a conversion layer, which is arranged on the TFT array substrate and converts radiation into light; and a conductive cover, which covers the conversion layer, wherein the conductive cover is adhered in an adhesion area in an upper layer than an area, in which at least one of the data line and the bias line extend from the pixel area to each of terminals, and wherein inorganic insulation films configured by at least two layers are formed between the at least one of the data line and the bias line and the adhesion area. | 06-06-2013 |
20130271717 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention includes liquid crystal held between an array substrate including a display area and a color filter substrate, a seal material pasting the both substrates together outside in plan view of the display area, and column spacers between the both substrates. The seal material includes a seal periphery surrounding the display area, and seal extending portions forming an injection port of the liquid crystal by extending the seal periphery outside in plan view of the display area from both end of a partial opening. The seal periphery includes no spacer therein, and the seal extending portions include spacers therein. | 10-17-2013 |
Patent application number | Description | Published |
20090109875 | Network Topology Management System, Management Apparatus, Management Method, Management Program, and Storage Media That Records Management Program - A network topology management system includes information processing units, storage units, connection units that control connection switching between the information processing units and the storage units, a management unit that manages a network topology consisting of the information processing units, the storage units and the connection units, and an emulator connected to the connection units and to the management unit the network. The emulator comprises a conversion section that converts first equipment identification information that identifies the information processing units or the storage units into second equipment identification information that is recognizable by the management unit to identify the information processing units or the storage units, and a transmitting section that sends the second equipment identification information to the management unit. The management device has a control section that manages the network topology based on the second equipment identification information. | 04-30-2009 |
20100274880 | Network Topology Management System, Management Apparatus, Management Method, Management Program, and Storage Media That Records Management Program - A network topology management system includes information processing units, storage units, connection units that control connection switching between the information processing units and the storage units, a management unit that manages a network topology consisting of the information processing units, the storage units and the connection units, and an emulator connected to the connection units and to the management unit the network. The emulator comprises a conversion section that converts first equipment identification information that identifies the information processing units or the storage units into second equipment identification information that is recognizable by the management unit to identify the information processing units or the storage units, and a transmitting section that sends the second equipment identification information to the management unit. The management device has a control section that manages the network topology based on the second equipment identification information. | 10-28-2010 |
20110055528 | DATA PROCESSOR - The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains. For example, in case that the domain manager performs data transfer between domains in the enhanced access mode, a read access from the domain manager is disguised as a read access from a first domain, and a write access from the domain manager is disguised as a write access from a second domain. | 03-03-2011 |
20110131577 | DATA PROCESSOR - This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated. | 06-02-2011 |
20110161644 | INFORMATION PROCESSOR - When a plurality of OSs are mounted, it is desirable to efficiently use memory resources without affecting other OSs. Also, even if the OSs are different from each other, they are mounted on one system, and therefore, inter-OS communication is required. In this case, data communication without affecting other OSs is required. Accordingly, an information processor includes: a firmware for assigning a first central processing unit, a first operating system, and a first region being a partial region of a memory as a first domain, assigning a second central processing unit, a second operating system, and a second region being a partial region of the memory as a second domain, and controlling to disable an access of one domain to a region assigned for the other domain; and a middleware for controlling a communication when the data communication is required between the first domain and the second domain. Further, when a sharable code is available in the operating systems, the code is stored in a region of the memory to which only a read access of each domain is enabled. Still further, when the communication is executed between the domains, with a state that the access to the memory region for the communication is limited by the middleware and the firmware, each domain accesses the region. | 06-30-2011 |
20130111492 | Information Processing System, and Its Power-Saving Control Method and Device | 05-02-2013 |
20130191676 | OPERATION MANAGEMENT METHOD OF INFORMATION PROCESSING SYSTEM - Power saving of a data center is realized by learning a correlation between a state of cooling efficiency of the entire IT equipment units and a workload of each IT equipment unit from an operation history and placing a workload on an IT equipment unit by using the correlation. An IT workload placement optimization function samples data from an operation history of various IT equipment units in a server room by using three criteria of temperature, workload, and time, classifies the data into cooling efficiency conditions of the entire IT equipment units, and outputs a workload placement directive for determining placement of workload on each IT equipment unit from the correlation between the cooling efficiency condition and the workload to a workload management server, so that the workload management server can effectively extract influence on the cooling efficiency from the operation history and use the influence to place the workload. | 07-25-2013 |
20140002987 | INFORMATION PROCESSING SYSTEM, OPERATION MANAGEMENT METHOD OF INFORMATION PROCESSING SYSTEM, AND DATA CENTER | 01-02-2014 |