Patent application number | Description | Published |
20090040255 | INKJET PRINTER AND INKJET PRINTING METHOD - An image having high quality is output, in which density unevenness due to a deflection in an ejecting direction is reduced, in an inkjet printer for forming an image by ejecting small droplets at a high frequency and high density. Thereby, in a mask pattern employed for multi-pass printing, a print permission rate of an ejection port positioned at the end of a ejection port array is set higher than those of ejection ports positioned at the other parts of the ejection port array. Thus, even if extremely small droplets are ejected at a high frequency and high-density, the generated density unevenness is reduced, and an image excellent in uniformity and having high definition can be output at a high speed. | 02-12-2009 |
20090040550 | DATA GENERATION APPARATUS, PRINTING APPARATUS AND DATA GENERATION METHOD - When a feeding amount for multi-pass printing is changed, the purpose related to an image quality using a binary data generation pattern can still be attained by, for example, a density pattern method. Specifically, a multi-pass printing mode is identified, and a density pattern selection matrix associated with a cycle of binary data generation is selected in accordance with the selected printing mode. That is, a density pattern selection matrix employed for binary data generation using a density pattern is changed to a size corresponding to the feeding amount designated by the selected printing mode. Thereby, a phenomenon that a unit used for image processing to gain a predetermined purpose related to an image quality does not match a unit area used for a printing operation is avoided, and an image printing purpose using a binary data generation pattern can be appropriately attained. | 02-12-2009 |
20090184994 | DATA PROCESSING APPARATUS, PRINTING APPARATUS AND METHOD OF CREATING MASK PATTERN - The interference between the dot arrangement pattern used for binarizing an image and the mask pattern for processing the dot arrangement pattern can be reduced and the well dispersed dot arrangement can realized by using the mask pattern. Specifically, in creating the mask, repulsive potential between the mask and the plane of dots arrangement pattern is calculated. That is, when the arrangement of print permitting pixels in the mask is determined, repulsive potential between print permitting pixels and dots on the plane of the dot arrangement pattern is calculated and print permitting pixels are arranged on the position where energy is the lowest and most dispersed. This enables print permitting pixels to be well dispersed in overlapping of the dot arrangement pattern and the mask. Consequently, as to dots formed by mask-processing and each scanning, their number is not unequally high in a specific scanning and dots are well dispersed. | 07-23-2009 |
20090189934 | RECORDING APPARATUS AND RECORDING METHOD - A recording apparatus for recording an image on a recording medium by scanning the recording medium with a recording head for discharging ink includes a thinning unit configured to thin data for discharging ink by the recording head on a plurality of areas formed by dividing scanning regions including at least a first scanning region and a second scanning region to be recorded each by one scan of the recording head in the scan direction, and a recording head drive unit configured to discharge ink by driving the recording head based on data which has been thinned by the thinning unit, wherein a boundary between the areas in the first scanning region is located in a different position from that of a boundary between areas in the second scanning region, which is adjacent to the first scanning region, in the scan direction. | 07-30-2009 |
20100045723 | INK-JET PRINTING APPARATUS AND INK-JET PRINTING METHOD - The print permitting ratios of the masks in the first to fourth passes of a C ink are respectively 6.2%, 37.5%, 37.5%, and 18.8%. On the other hand, the print permitting ratios of the masks in the first to fourth passes of an M ink are respectively 12.5%, 37.5%, 37.5%, and 12.5%. In this way, the respective masks are set such that a larger amount of the C ink is applied in a later pass as compared with the M ink. Thereby, it is possible to reduce an amount of the M ink to be applied later with respect to the C ink functioning to “reduce a permeation speed of an ink applied later by filling,” and it is possible to prevent a permeation speed from slowing down overall. As a result, it is possible to prevent the occurrence of beading due to a time to complete permeation becoming longer. | 02-25-2010 |
20110019208 | IMAGE DATA GENERATING APPARATUS, PRINTING APPARATUS, AND IMAGE DATA GENERATION METHOD - When error diffusion processing is applied to thinned printing, the thinned printing can be performed without spoiling the dot printing pattern, and dot data is generated so that occurrence of grain may be suppressed by the dot arrangement distributed by the error diffusion processing. Specifically, the error diffusion of the binary data is performed in consideration of permitted positions shown by a division pattern of a nozzle array. That is, the binary data is permitted to be arranged only at a pixel position indicated by black in the division pattern of the nozzle array. Next, the result of having subtracted binary data from multi-valued data is applied as correction data of a multiple value, and this correction data is added to cyan multi-valued data of the nozzle array of first pass related to second plane generation. | 01-27-2011 |
20110181897 | DATA PROCESSOR, DATA PRCESSING METHOD AND PROGRAM - Provided are a data processing method and a data processor for ink jet printing, which are capable of achieving uniform and high-quality images while stabilizing density and color development in each of pixels. To this end, a mask pattern for setting permission and non-permission to print dots in each area is arranged non-periodically by using an integral multiple of m×n areas as one unit. The m×n areas allow one pixel to be expressed in half-tone. Thereby, density in the pixel is stable since a plurality of dots printed in the same pixel are printed approximately in the same event. Moreover, since each of the units (clusters) is non-periodically arranged, a uniform image can be obtained. | 07-28-2011 |
20110261373 | DATA GENERATION APPARATUS, PRINTING APPARATUS AND DATA GENERATION METHOD - When a feeding amount for multi-pass printing is changed, the purpose related to an image quality using a binary data generation pattern can still be attained by, for example, a density pattern method. Specifically, a multi-pass printing mode is identified, and a density pattern selection matrix associated with a cycle of binary data generation is selected in accordance with the selected printing mode. That is, a density pattern selection matrix employed for binary data generation using a density pattern is changed to a size corresponding to the feeding amount designated by the selected printing mode. Thereby, a phenomenon that a unit used for image processing to gain a predetermined purpose related to an image quality does not match a unit area used for a printing operation is avoided, and an image printing purpose using a binary data generation pattern can be appropriately attained. | 10-27-2011 |
20120262736 | DATA PROCESSOR, DATA PROCESSING METHOD AND PROGRAM - Provided are a data processing method and a data processor for ink jet printing, which are capable of achieving uniform and high-quality images while stabilizing density and color development in each of pixels. To this end, a mask pattern for setting permission and non-permission to print dots in each area is arranged non-periodically by using an integral multiple of m×n areas as one unit. The m×n areas allow one pixel to be expressed in half-tone. Thereby, density in the pixel is stable since a plurality of dots printed in the same pixel are printed approximately in the same event. Moreover, since each of the units (clusters) is non-periodically arranged, a uniform image can be obtained. | 10-18-2012 |
Patent application number | Description | Published |
20130027093 | PLL - One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value. | 01-31-2013 |
20130268795 | CACHE SYSTEM AND INFORMATION-PROCESSING DEVICE - According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit. | 10-10-2013 |
20130301345 | MAGNETIC RANDOM ACCESS MEMORY AND MEMORY SYSTEM - According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected. | 11-14-2013 |
20130322161 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential. | 12-05-2013 |
20140104920 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps. | 04-17-2014 |
20140281189 | PROCESSOR SYSTEM HAVING VARIABLE CAPACITY MEMORY - According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2 | 09-18-2014 |
20140293685 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a plurality of memory cells, each memory cell including a first MTJ element and a first selection unit; a pair of a first and second bit lines provided to each column of the memory cells; a word line provided to each row of the memory cells; an equalizer circuit provided to each column of the memory cells, and to connect between the first and second bit lines; and a control circuit that sets the first and second bit lines connected to a selected memory cell to be a first and second potentials to conduct a write operation, and after the write operation, transmits a control signal to the equalizer circuit between the first and second bit lines to activate the equalizer circuit to equalize potentials of the first bit line and the second bit line, thereby bringing into floating states. | 10-02-2014 |
20140339616 | NON-VOLATILE MEMORY, WRITING METHOD FOR THE SAME, AND READING METHOD FOR THE SAME - A non-volatile memory of an embodiment includes a plurality of memory cells, each of the memory cells including a plurality of transistors including a first to fourth transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the first and second transistors being connected in series with the first non-volatile element, the third and fourth transistors being connected in series with the second non-volatile element, the first node being disposed between the first and second transistors, the second node being disposed between the third and fourth transistors, gates of the first and third transistors being connected to one of first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of second wiring lines and the first node. | 11-20-2014 |
20140379975 | PROCESSOR - According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas. | 12-25-2014 |
Patent application number | Description | Published |
20120288005 | MOTION VECTOR CORRECTION DEVICE AND METHOD AND VIDEO SIGNAL PROCESSING APPARATUS AND METHOD - A motion vector detector | 11-15-2012 |
20130051470 | MOTION COMPENSATED FRAME GENERATING APPARATUS AND METHOD - A motion vector detector detects a motion vector, and outputs a block matching error value. An entire scroll determiner generates an entire scroll degree. Based on the block matching error value, a reliability generator generates reliability data indicating reliability of the motion vector. A reliability adjuster adjusts the reliability data so that a value of the reliability data is larger as the entire scroll degree is a value in which the degree at which the image scrolls entirely is larger, and outputs adjusted reliability data. Based on the adjusted reliability data, the interpolation pixel generator generates respective interpolation pixels composing a motion compensated frame. | 02-28-2013 |
20130194385 | STEREOSCOPIC IMAGE GENERATION APPARATUS AND STEREOSCOPIC IMAGE GENERATION METHOD - A 3D parallax value detection unit detects a parallax value between a left-eye image signal and a right-eye image signal in a stereoscopic video signal. A stereoscopic degree determination unit determines a stereoscopic degree of the stereoscopic video signal based on the parallax value. In response to the stereoscopic degree, an image signal conversion unit obtains an amount of pixel shift, by which a pixel of the left-eye image signal or the right-eye image signal is to be shifted, and shifts the pixel by the amount of pixel shift. In such a way, a parallax of the left-eye image signal or the right-eye image signal is adjusted. | 08-01-2013 |
20130242047 | DEPTH SIGNAL GENERATION APPARATUS, PSEUDO STEREO IMAGE SIGNAL GENERATION APPARATUS, DEPTH SIGNAL GENERATION METHOD, PSEUDO STEREO IMAGE SIGNAL GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM RECORDING DEPTH SIGNAL GENERATION PROGRAM, AND COMPUTER-READABLE RECORDING MEDIUM RECORDING PSEUDO STEREO IMAGE SIGNAL GENERATION PROGRAM - A depth signal generation apparatus includes a depth signal estimation unit, a depth signal histogram generator, and a depth signal level converter. The depth signal estimation unit estimates a depth signal for each pixel of a predetermined unit in a video image signal. The depth signal histogram generator divides a range of a depth signal level which the depth signal can have, into depth signal level regions each having a predetermined range size, determines which depth signal level region includes the depth signal for each pixel, counts the number of pixels included in each depth signal level region to generate depth signal histogram data according to the count value. The depth signal level converter generates a depth signal level conversion curve according to the depth signal histogram data and generates a depth signal after level conversion by executing depth signal level conversion according to the depth signal level conversion curve. | 09-19-2013 |
20130265390 | STEREOSCOPIC IMAGE DISPLAY PROCESSING DEVICE, STEREOSCOPIC IMAGE DISPLAY PROCESSING METHOD, AND STEREOSCOPIC IMAGE DISPLAY PROCESSING PROGRAM - A decoding section outputs a display image signal based on an input processed image signal after executing 3D decoding processing of the processed image signal based on a 3D format of the processed image signal, or without executing the 3D decoding processing. A determination section determines a state of superimposed text information in the processed image signal. A control section controls the decoding section to execute or not to execute the 3D decoding processing of the processed image signal based on a determination result from the determination section. | 10-10-2013 |
Patent application number | Description | Published |
20100245862 | IMAGE-PROCESSING DEVICE, IMAGE-FORMING DEVICE, IMAGE-PROCESSING METHOD, AND COMPUTER READABLE MEDIUM - An image-processing device includes: an obtaining unit that obtains image data; an area extraction unit that extracts an area having a color falling within a predetermined range of a color, in an image represented by the image data obtained by the obtaining unit; a component extraction unit that extracts a component meeting a predetermined condition on a component of an image, in the image represented by the image data obtained by the obtaining unit; and a generating unit that if a component is extracted by the component extraction unit, that meets the predetermined condition, generates image data representing an image in which an effect of a type associated with the predetermined condition is applied to the area extracted by the area extraction unit. | 09-30-2010 |
20100246943 | IMAGE-PROCESSING DEVICE, IMAGE-FORMING DEVICE, AND STORING MEDIUM - An image-processing device includes: a memory that stores a red range occurring within a color space; an acquisition unit that acquires image data representing a document image that includes characters; and a production unit that produces image data representing an overall image that includes: the document image represented by the image data that is acquired by the acquisition unit, a differentiation image that is positioned within the document image and that allows the user to differentiate an image of red characters residing in the range from an image formed of colors other than red, and an information image representing information for acquiring the document image in a state in which the differentiation image is not positioned. | 09-30-2010 |
20150026639 | INFORMATION PROCESSING APPARATUS AND METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - An information processing apparatus includes an image display unit, an arrangement unit, and a marker display unit. The image display unit displays images. Upon acceptance of an instruction to rearrange an image selected from among the images in an arrangement area including one of the images, the arrangement unit rearranges the selected image at a rearrangement position in the arrangement area on the image display unit. The marker display unit displays a marker image between an image at the rearrangement position and an image arranged lower in rank than the image at the rearrangement position when the rearrangement position is lower than the position of the selected image, or displays the marker image between the image at the rearrangement position and an image arranged higher in rank than the image at the rearrangement position when the rearrangement position is higher than the position of the selected image. | 01-22-2015 |
Patent application number | Description | Published |
20080292282 | Input-output circuit, recording apparatus and reproduction apparatus for digital video signal - A video signal input-output circuit and a recording-reproduction apparatus in which a digitally compressed video signal input in packet form can be recorded and reproduced efficiently and in stable fashion. In this apparatus, a clock reference is detected from a packet signal containing the clock reference and a digitally compressed video signal, a time stamp for a packet is generated using a clock signal in phase with the clock reference and added to the particular packet, and the packet signals with the time stamp added thereto are recorded closely to each other in a data storage element such as a magnetic recording medium. At playback, the packet interval is output by being restored to the original length on the basis of the time stamp added to the packet in store. | 11-27-2008 |
20080292283 | Input-output circuit, recording apparatus and reproduction apparatus for digital video signal - A video signal input-output circuit and a recording-reproduction apparatus in which a digitally compressed video signal input in packet form can be recorded and reproduced efficiently and in stable fashion. In this apparatus, a clock reference is detected from a packet signal containing the clock reference and a digitally compressed video signal, a time stamp for a packet is generated using a clock signal in phase with the clock reference and added to the particular packet, and the packet signals with the time stamp added thereto are recorded closely to each other in a data storage element such as a magnetic recording medium. At playback, the packet interval is output by being restored to the original length on the basis of the time stamp added to the packet in store. | 11-27-2008 |
20090003803 | Input-output circuit, recording apparatus and reproduction apparatus for digital video signal - A video signal input-output circuit and a recording-reproduction apparatus in which a digitally compressed video signal input in packet form can be recorded and reproduced efficiently and in stable fashion. In this apparatus, a clock reference is detected from a packet signal containing the clock reference and a digitally compressed video signal, a time stamp for a packet is generated using a clock signal in phase with the clock reference and added to the particular packet, and the packet signals with the time stamp added thereto are recorded closely to each other in a data storage element such as a magnetic recording medium. At playback, the packet interval is output by being restored to the original length on the basis of the time stamp added to the packet in store. | 01-01-2009 |
20090252478 | METHOD AND APPARATUS FOR RECEIVING A DIGITAL SIGNAL AND APPARATUS FOR RECORDING AND REPRODUCING THE DIGITAL SIGNAL - A method and apparatus is provided for receiving and/or reproducing a digital signal, capable of efficiently recording a compressed, packeted digital signal and inhibiting a copy thereof. An input packet signal is added with a time stamp indicating a relative time of an arrival of the packet, and the packet signals of digital information with the added time stamps are recorded at reduced intervals therebetween. In reproducing, a packet interval adjusting circuit restores the original packet intervals in accordance with the time stamps, and then a time stamp change circuit changes at least one bit of the time stamp and thereafter outputs the digital information. | 10-08-2009 |
20100027962 | INPUT-OUTPUT CIRCUIT, RECORDING APPARATUS AND REPRODUCTION APPARATUS FOR DIGITAL VIDEO SIGNAL - A video signal input-output circuit and a recording-reproduction apparatus in which a digitally compressed video signal input in packet form can be recorded and reproduced efficiently and in stable fashion. In this apparatus, a clock reference is detected from a packet signal containing the clock reference and a digitally compressed video signal, a time stamp for a packet is generated using a clock signal in phase with the clock reference and added to the particular packet, and the packet signals with the time stamp added thereto are recorded closely to each other in a data storage element such as a magnetic recording medium. At playback, the packet interval is output by being restored to the original length on the basis of the time stamp added to the packet in store. | 02-04-2010 |
20130163964 | METHOD OF USING AV DEVICES AND AV DEVICE SYSTEM - A plurality of devices and a device system are disclosed, in which a plurality of input devices generate an input AV signal, a related device records and reproduces the AV signal, and a display device displays the AV signal. The input devices, the related device and the display device are interconnected to configure an AV system having a bus for transmitting or receiving the AV signal and management information. The related device of the AV system includes a recording medium for recording the AV signal, and the input devices transmit to the related device a request to secure a recording area on the recording medium. | 06-27-2013 |