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Nobuyoshi Takahashi

Nobuyoshi Takahashi, Toyama JP

Patent application number	Description	Published
20090052250	SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines and the plurality of bit lines. Each word line provides a first gate electrode in the corresponding memory element. A lower portion of a side surface of each word line in a direction parallel to an extending direction of the word line is perpendicular to a main surface of the semiconductor region. An upper portion of the side surface is inclined so that a width thereof becomes smaller toward a top thereof.	02-26-2009
20090057767	SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a protected device formed on a semiconductor substrate, a first protection transistor formed in a second well of a second conductivity type, and a second protection transistor formed in a first well of a first conductivity type. A fourth source/drain diffusion layer of the second protection transistor is in contact with a second diffusion layer, and a third source/drain diffusion layer is in contact with a second source/drain diffusion layer of the first protection transistor in the second well. A first source/drain diffusion layer of the first protection transistor is in contact with a first diffusion layer, which is in contact with a protected device electrode.	03-05-2009
20090189214	SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films s formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity.	07-30-2009
20090256232	SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.	10-15-2009
20110021013	SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.	01-27-2011
20110084277	SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines and the plurality of bit lines. Each word line provides a first gate electrode in the corresponding memory element. A lower portion of a side surface of each word line in a direction parallel to an extending direction of the word line is perpendicular to a main surface of the semiconductor region. An upper portion of the side surface is inclined so that a width thereof becomes smaller toward a top thereof.	04-14-2011

Nobuyoshi Takahashi, Niigata JP

Patent application number	Description	Published
20090321814	SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor memory device includes, in a memory region, a plurality of bit line diffusion layers, a plurality of word lines, and a plurality of memory elements composed of a bit line diffusion layer pair, a gate insulating film, and a gate electrode. The plurality of bit line diffusion layers are divided into plural in respective columns, and are connected electrically to each other through bit line contact diffusion layers. The width of sidewall insulating films on the sides of the bit line contact diffusion layers formed at the word lines arranged adjacent to the bit line contact diffusion layers is smaller than that of the sidewall insulating films formed on the opposite sides of the bit line contact diffusion layers.	12-31-2009
20100213987	SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD FOR THE SAME - A semiconductor device includes an element to be protected formed on a semiconductor substrate, a first protection transistor, and a second protection transistor. The first protection transistor is formed on a first well of a first conductivity type formed in an upper portion of a deep well of a second conductivity type. The second protection transistor is formed on a second well of the second conductivity type. A second source/drain diffusion layer is electrically connected with a third source/drain diffusion layer and at the same potential as the first well. A fourth source/drain diffusion layer is electrically connected with a second diffusion layer and at the same potential as the second well and the second diffusion layer.	08-26-2010

Nobuyoshi Takahashi, Nara JP

Patent application number	Description	Published
20090104765	SEMICONDUCTOR DEVICE HAVING DIFFUSION LAYERS AS BIT LINES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.	04-23-2009
20090317955	SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.	12-24-2009

Nobuyoshi Takahashi, Saitama JP

Patent application number	Description	Published
20110158869	PROCESSING METHOD FOR RECOVERING IRON OXIDE AND HYDROCHLORIC ACID - A method of processing waste iron chloride solution including ferrous chloride, ferric chloride or mixtures thereof and optionally free hydrochloric acid, includes concentrating waste iron chloride solution into concentrated liquid having iron chloride concentration of at least 30%-40% by weight; optionally oxidizing ferrous chloride in the concentrated liquid from the concentration step to ferric chloride providing liquid containing ferric chloride; hydrolyzing the liquid containing ferric chloride from the oxidation step at 155-350° C., maintaining the ferric chloride concentration at least at 65% by weight, generating steam containing hydrogen chloride and liquid containing ferric oxide; separating ferric oxide from the liquid containing ferric oxide in the hydrolysis step; condensing steam containing hydrogen chloride in the hydrolysis step, recovering hydrochloric acid at a concentration of at least 10%-15% by weight; and using condensation energy of the hydrogen chloride containing steam in the recovery step to heat the concentration step performed under reduced pressure.	06-30-2011