Patent application number | Description | Published |
20090042403 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of forming a nitrogen-containing layer in an exposed portion of a copper interconnect formed in an insulating film provided on a substrate; and forming an interlayer insulating film on the nitrogen-containing layer through plasma CVD performed by using, as a material, an organic silicon compound having a siloxane (Si—O—Si) bond. | 02-12-2009 |
20090098726 | METHOD FOR FORMING INLAID INTERCONNECT - After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer. | 04-16-2009 |
20090266590 | INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME - An interconnect structure includes: an interlayer insulating film formed on a lower metal layer; a contact hole formed in the interlayer insulating film to expose the lower metal layer; a plurality of carbon nanotubes formed on a bottom of the contact hole; an wiring metal filled in the contact hole to fill gap between the plurality of carbon nanotubes; and an upper wiring formed above the contact hole. A Ti layer is formed between the plurality of carbon nanotubes and the upper wiring. | 10-29-2009 |
20090298298 | METHOD OF FORMING INTERLAYER INSULATING FILM, PRECURSOR SOLUTION FOR FORMING OF INTERLAYER INSULATING FILM, CVD MATERIAL FOR FORMING OF INTERLAYER INSULATING FILM AND RAW MATERIAL FOR PRODUCTION OF SILOXANE OLIGOMER - In a method of forming an interlayer insulating film by plasma CVD, an organic siloxane compound including one or more silicon atoms each having at least three or more units each represented by a general formula, —O—Si(R | 12-03-2009 |
20100087059 | METHOD FOR FORMING INLAID INTERCONNECT - After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer. | 04-08-2010 |
20100102449 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In a semiconductor device including: an insulating film ( | 04-29-2010 |
20100167467 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - At least three or more plurality of chips are stacked to form a three-dimensional integrated circuit. When the plurality of chips are stacked, at least two or more of three stacking methods are used which are a wafer-to-wafer stacking method that bonds together the mutually corresponding chips each on a wafer level, a chip-to-wafer stacking method that bonds together the mutually corresponding chips including one on a chip level and the other on a wafer level, and a chip-to-chip stacking method that bonds together the mutually corresponding chips each on a chip level. | 07-01-2010 |
20100171218 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first substrate formed with a through silicon via reaching the back surface thereof, and a second substrate electrically connected to the first substrate via the through silicon via, and bonded to the back surface of the first substrate. A taper angle of a sidewall of a tip end portion of the through silicon via connected to the second substrate is larger than a taper angle of a sidewall of the other portion thereof. | 07-08-2010 |
20130140680 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an active region located in an upper portion of a semiconductor substrate; a through-hole electrode penetrating the substrate, and made of a conductor having a thermal expansion coefficient larger than that of a material for the substrate; and a stress buffer region located in the upper portion of the substrate and sandwiched between the through-hole electrode and the active region. The stress buffer region does not penetrate the substrate and includes a stress buffer part made of a material having a thermal expansion coefficient larger than that of the material for the substrate and an untreated region where the stress buffer part is not present. The stress buffer part is located in at least two locations sandwiching the untreated region in a cross section perpendicular to a surface of the substrate and passing through the through-hole electrode and the active region. | 06-06-2013 |
20130140696 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first substrate; a plurality of first electrodes formed on the first substrate; and a first insulating film formed on sidewalls of the plurality of first electrodes. The first insulating film is formed not to fill spaces between the plurality of first electrodes. | 06-06-2013 |
20140327157 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip. | 11-06-2014 |