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Nobuhiro Nonogaki
Nobuhiro Nonogaki, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090193220 | MEMORY MANAGEMENT DEVICE APPLIED TO SHARED-MEMORY MULTIPROCESSOR - A plurality of processors are capable of parallel operation. A memory is shared by the plurality of processors. The memory has an allocated memory size indicating the size of an area allocated to an allocatable area in the memory at the request of one of the plurality of processors and a deallocated memory size indicating the size of a deallocated area in the allocated area. One of the plurality of processors compares the allocated memory size with the deallocated memory size, thereby determining whether the memory is reusable. | 07-30-2009 |
| 20090254710 | DEVICE AND METHOD FOR CONTROLLING CACHE MEMORY - A cache memory control device according to an embodiment of the present invention comprises: a refill counter that counts a refill request, and a cache-capacity determining unit that determines cache capacity. The cache-capacity determining unit transmits a cache-capacity-decrease command signal to the cache memory when a count value is equal to or smaller than a first threshold value or is smaller than the first threshold value, and the cache-capacity determining unit transmits a cache-capacity-increase command signal to the cache memory when the count value is equal to or larger than a second threshold value, which is larger than the first threshold value, or when the count value is larger than the second threshold value. | 10-08-2009 |
| 20100118960 | IMAGE DECODING APPARATUS, IMAGE DECODING METHOD, AND IMAGE DATA CONVERTING APPARATUS - An image decoding apparatus includes a syntax-element compressing unit that executes compression processing on syntax elements extracted in syntax analysis processing and classifies the syntax elements based on types thereof, a plurality of syntax-element expanding units that correspond to any one of classified groups of syntax elements in a one to one relation and expand the syntax elements belonging to the corresponding group to restore the original syntax elements, and a plurality of signal processing units that correspond to any one of the syntax-element expanding units in a one to one relation and apply, to the syntax elements restored by the corresponding syntax-element expanding unit, signal processing corresponding to a type thereof. | 05-13-2010 |
| 20110061058 | TASK SCHEDULING METHOD AND MULTI-CORE SYSTEM - A task scheduling method and multi-core system according to an embodiment of the present invention comprises: in scheduling for selecting a task that is set in an execution state with a microprocessor allocated thereto out of tasks in an executable state, it is determined whether at least one of the tasks in a young generation, for which the number of times of refill performed until a point of scheduling after transitioning from the execution state to a standby state according to release of the microprocessor is smaller than a predetermined number of times, is present and, when at least one of the tasks in the young generation is present, microprocessor is allocated to the task selected from at least one of the tasks of the young generation. | 03-10-2011 |
Nobuhiro Nonogaki, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20080215817 | MEMORY MANAGEMENT SYSTEM AND IMAGE PROCESSING APPARATUS - A memory management system includes a plurality of processors, a shared memory that can be accessed from the plurality of processors, cache memories provided between each processor of the plurality of processors and the shared memory and invalidation or write back of a specified region can be commanded from a program running on a processor. Programs running on each processor invalidate an input data region of a cache memory with an invalidation command immediately before execution of a program as a processing batch, and write back an output data region of a cache memory to the shared memory with a write back command immediately after execution of a program as a processing batch. | 09-04-2008 |
| 20100241920 | IMAGE DECODING APPARATUS, IMAGE DECODING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - An image decoding apparatus is an image decoding apparatus that parses an input bit stream to extract decode parameters and generates a decoded image based on the decode parameters. The image decoding apparatus includes: an error position/recovery position detecting unit that detects an error position and a recovery position in the decode parameters and discards the decode parameters in the error position to the recovery position; and an interpolated-decode-parameter inserting unit that interpolates the decode parameters discarded by the error position/recovery position detecting unit. | 09-23-2010 |
Nobuhiro Nonogaki, Kanagawa-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20090244364 | MOVING IMAGE SEPARATING APPARATUS, MOVING IMAGE UNITING APPARATUS, AND MOVING IMAGE SEPARATING-UNITING SYSTEM - A moving image separating apparatus is disclosed. The apparatus is provided with a privacy image region detection unit and a moving image separating unit. The privacy image region detection unit detects privacy image region data indicating a position and a range of a privacy image region from the original moving image data. The moving image separating unit receives the original moving image data and the privacy image region data from the privacy image region detection unit. The moving image separating unit separates the original moving image data to private moving image data composed of image data corresponding to the privacy image region and to public moving image data composed of image data of a region excluding the privacy image region, on the basis of the privacy image region data. | 10-01-2009 |
Nobuhiro Nonogaki, Kawasaki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20080297522 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - An image processing apparatus has a memory in which a plurality of image processing commands are stored, a dependent information producing unit which produces dependent information in each image data block becoming a target image processing, the dependent information indicating a dependency relationship between image processing of the image data block and another processing, a dependency relationship solving unit which makes a determination of a practicable image processing based on the dependent information, the dependency relationship solving unit writing an image processing command of the practicable image processing in the memory, and a plurality of image processing units which read an image processing command stored in the memory, the image processing units performing the image processing to the image data block based on the image processing command. | 12-04-2008 |