Patent application number | Description | Published |
20080285360 | Semiconductor Memory Device and Method of Reading Data Therefrom - A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit. | 11-20-2008 |
20090010044 | Toggle Magnetic Random Access Memory and Write Method of Toggle Magnetic Random Access Memory - A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area. | 01-08-2009 |
20090122597 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM is provided with a memory main body ( | 05-14-2009 |
20090125787 | Operation Method of Mram - An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits. | 05-14-2009 |
20090141544 | Mram and Operation Method of the Same - An operation method of an MRAM of the present invention is an operation method of the MRAM in which a data write operation is carried out in a toggle write. The operation method of the present invention includes: (A) reading a data from a data cell by using a reference signal which is generated by using a reference cell; (B) performing an error detection on the read data; (C) correcting the data stored in the data cell, when an error is detected in the read data; (D) reading the data from the data cell as a first re-read data after the (C), when the error is detected in the read data, (E) performing the error detection on the first re-read data; (F) correcting the data stored in the reference cell, when an error is detected in the first re-read data; (G) reading the data from the data cell as a second re-read data after the (F), when the error is detected in the first re-read data; (H) performing the error detection on the second re-read data; and (I) correcting the data stored in the data cell again, when the error is detected in the second re-read data. | 06-04-2009 |
20090161423 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM having a first cell array group ( | 06-25-2009 |
20090262571 | Magnetic random access memory and operating method of magnetic random access memory - A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. The memory cell is provided correspondingly to an intersection between the first and second wirings and the third wiring. The terminating unit is provided between the plurality of memory cells and connected to the first and second wirings. The memory cell includes transistors and a magnetoresistive element. The transistors are connected in series between the first and second wirings and controlled based on a signal of the third wiring. The magnetoresistive element is connected to a wiring through which the transistors are connected. At a time of a writing operation, when the write current Iw is supplied from one of the first and second wiring to the other through the transistors, the terminating unit grounds the other. | 10-22-2009 |
20090296454 | MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory cell | 12-03-2009 |
20100046284 | MRAM - An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells. Respective data stored in the plurality of magnetic memory cells become the same when the offset adjustment magnetic field is removed. | 02-25-2010 |
20100097108 | SEMICONDUCTOR DEVICE - A semiconductor device having a nonvolatile variable resistor, includes: a resistance value conversion circuit unit configured to convert a resistance value of the nonvolatile variable resistor into a potential or a current and which outputs the converted potential or current; a comparison circuit unit configured to compare the output from the resistance value conversion circuit unit and a potential or current at a node of a portion within the semiconductor device; and a resistance value changing circuit unit configured to change the resistance value of the nonvolatile variable resistor based on the comparison results from the comparison circuit unit. | 04-22-2010 |
20100097845 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided with a memory array including a plurality of memory cells. The plurality of memory cells includes: first and third memory cells arranged along one of an even-numbered row and an odd-numbered row, and a second memory cell arranged along the other. Each of the plurality of memory cells includes: a first transistor comprising first and second diffusion layers; a second transistor comprising third and fourth diffusion layers; and a magnetoresistance element having one of terminals thereof connected to an interconnection layer which provides an electrical connection between the second and third diffusion layers. The fourth diffusion layer of the first memory cell is also used as the first diffusion layer of the second memory cell. In addition, the fourth diffusion layer of the second memory cell is also used as the first diffusion layer of the third memory cell. | 04-22-2010 |
20100177558 | MRAM HAVING VARIABLE WORD LINE DRIVE POTENTIAL - An MRAM of a spin transfer type according to the invention is provided with a memory cell | 07-15-2010 |
20100182824 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor. The other end of the magnetoresistance element is connected to the second word line. | 07-22-2010 |
20100238719 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATING METHOD OF THE SAME - A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line. | 09-23-2010 |
20100265760 | NONVOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT USING THE SAME - A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit. | 10-21-2010 |
20100271866 | NONVOLATILE LATCH CIRCUIT - A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element. | 10-28-2010 |
20110016371 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF OPERATING THE SAME - Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells | 01-20-2011 |
20110148458 | MAGNETORESISTIVE ELEMENT, LOGIC GATE AND METHOD OF OPERATING LOGIC GATE - A logic gate | 06-23-2011 |
20120063199 | SEMICONDUCTOR DEVICE - A semiconductor device having a nonvolatile variable resistor, includes: a resistance value conversion circuit unit configured to convert a resistance value of the nonvolatile variable resistor into a potential or a current and which outputs the converted potential or current; a comparison circuit unit configured to compare the output from the resistance value conversion circuit unit and a potential or current at a node of a portion within the semiconductor device; and a resistance value changing circuit unit configured to change the resistance value of the nonvolatile variable resistor based on the comparison results from the comparison circuit unit. | 03-15-2012 |
20120206959 | MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory cell | 08-16-2012 |
20130181739 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE CONTROL METHOD - A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit. | 07-18-2013 |
20130182501 | SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURING METHOD - A magnetoresistive element | 07-18-2013 |
20140233304 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction. | 08-21-2014 |
20140313843 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREFOR - A semiconductor integrated circuit includes a plurality of first non-volatile registers including a retention circuit that retains volatile data and one or more non-volatile elements capable of retaining non-volatile data, and a second non-volatile register that retains a load enable bit that decides in which one of the plurality of first non-volatile registers data is loaded. The semiconductor integrated circuit also includes a non-volatile register control circuit that, when supply power is delivered from outside, loads to the retention circuit data retained by the non-volatile element(s) contained in the first non-volatile register specified by the load enable bit loaded from the second non-volatile register (FIG. | 10-23-2014 |
20150042376 | NONVOLATILE RESISTOR NETWORK ASSEMBLY AND NONVOLATILE LOGIC GATE WITH INCREASED FAULT TOLERANCE USING THE SAME - Provided is a nonvolatile resistor network assembly characterized by that: it comprises a first and a second resistor network which are each composed of a plurality of nonvolatile resistive elements connected together; it also comprises a write means for writing into the first and second resistor networks; and writing into the first and second resistor networks is performed by the use of the write means in a manner to make total resistances of respectively the first and second resistor networks different from each other. Further provided is a nonvolatile logic gate which performs logical operation using stored data determined by the total resistances of the respective nonvolatile resistor networks. | 02-12-2015 |
20150048680 | SEMICONDUCTOR DEVICE, POWER SUPPLY CONTROL METHOD OF SEMICONDUCTOR DEVICE, AND SENSOR NODE - A semiconductor device includes a current control unit whose conductance is variable and a control unit configured to control the conductance of the current control unit. The current control unit is connected to a direct current power source in parallel with a load for the direct current power source, through a capacitor. The control unit sets the current control unit to a first conductance when the direct current power source and the load are not in a conduction state, and sets the current control unit to a second conductance larger than the first conductance when the direct current power source and the load are in the conduction state. | 02-19-2015 |