Patent application number | Description | Published |
20090042401 | COMPOSITIONS AND METHODS FOR SUBSTANTIALLY EQUALIZING RATES AT WHICH MATERIAL IS REMOVED OVER AN AREA OF A STRUCTURE OR FILM THAT INCLUDES RECESSES OR CREVICES - Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed. | 02-12-2009 |
20090056746 | Methods For Treating Surfaces, And Apparatuses For Treating Surfaces - Some embodiments include methods of treating surfaces with aerosol particles. The aerosol particles may be formed as liquid particles, and then passed through a chamber under conditions which change the elasticity of the particles prior to impacting a surface with the particles. The change in elasticity may be an increase in the elasticity, or a decrease in the elasticity. The change in elasticity may be accomplished by causing a phase change of one or more components of the aerosol particles such as, for example, by at least partially freezing the aerosol particles, or by forming entrained bubbles within the aerosol particles. Some embodiments include apparatuses that may be utilized during treatment of surfaces with aerosol particles. | 03-05-2009 |
20090074950 | Methods of Forming Charge-Trapping Regions - Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells. | 03-19-2009 |
20090090692 | Methods of Processing Substrates and Methods of Forming Conductive Connections to Substrates - Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material. | 04-09-2009 |
20090114246 | Methods For Treating Surfaces - Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer layer may be formed across a surface. The dispersion may be directed toward the transfer layer, and the insolubles may impact the transfer layer. The impacting may generate force in the transfer layer, and such force may be transferred through the transfer layer to the surface. The surface may be a surface of a semiconductor substrate, and the force may be utilized to sweep contaminants from the semiconductor substrate surface. The transfer layer may be a liquid, and in some embodiments may be a cleaning solution. | 05-07-2009 |
20090173358 | MEGASONIC CLEANING WITH CONTROLLED BOUNDARY LAYER THICKNESS AND ASSOCIATED SYSTEMS AND METHODS - Megasonic cleaning systems and methods of using megasonic pressure waves to impart cavitation energy proximate a surface of a microelectronic substrate are disclosed herein. In one embodiment, a megasonic cleaning system includes a process tank for containing a liquid, a support element for carrying a substrate submerged in the liquid, and first and second transducers positioned in the tank. The first transducer is further positioned and/or operated to initiate cavitation events in a bulk portion of the liquid proximate a surface of the substrate. The second transducer is further positioned and/or operated to control an interface of fluid friction between the substrate and the bulk portion of the liquid. | 07-09-2009 |
20090211595 | Rheological fluids for particle removal - Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided. | 08-27-2009 |
20090238958 | Methods of Forming Electrically Conductive Structures - Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings. | 09-24-2009 |
20090253271 | SPIN-ON FILM PROCESSING USING ACCOUSTIC RADIATION PRESSURE - An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure to alter the liquid topography. Other apparatus and processes are disclosed. | 10-08-2009 |
20090263729 | TEMPLATES FOR IMPRINT LITHOGRAPHY AND METHODS OF FABRICATING AND USING SUCH TEMPLATES - A template for use in imprint lithography is disclosed. The template includes at least two ultraviolet transparent materials bonded together by an ultraviolet transparent epoxy. The ultraviolet transparent epoxy is a polymeric, spin-on epoxy or a two-part, amine-cured epoxy having a viscosity at room temperature of from about 35,000 cps to about 45,000 cps. The template has a substantially uniform index of refraction. Additionally, methods of forming and using the templates are disclosed. | 10-22-2009 |
20090275208 | Compositions of Matter, and Methods of Removing Silicon Dioxide - Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX | 11-05-2009 |
20100003782 | Methods Of Forming A Non-Volatile Resistive Oxide Memory Cell And Methods Of Forming A Non-Volatile Resistive Oxide Memory Array - A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated. | 01-07-2010 |
20100013107 | INTERCONNECT STRUCTURES FOR INTEGRATION OF MULTI-LAYERED INTEGRATED CIRCUIT DEVICES AND METHODS FOR FORMING THE SAME - Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed. | 01-21-2010 |
20100025854 | POLISHING SYSTEMS AND METHODS FOR REMOVING CONDUCTIVE MATERIAL FROM MICROELECTRONIC SUBSTRATES - Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material. | 02-04-2010 |
20100043824 | MICROELECTRONIC SUBSTRATE CLEANING SYSTEMS WITH POLYELECTROLYTE AND ASSOCIATED METHODS - Several embodiments of cleaning systems using polyelectrolyte and various associated methods for cleaning microelectronic substrates are disclosed herein. One embodiment is directed to a system that has a substrate support for holding the microelectronic substrate, a dispenser positioned above the substrate support and facing a surface of the microelectronic substrate, a reservoir in fluid communication with the dispenser via a conduit, and a washing solution contained in the reservoir. The washing solution includes a polyelectrolyte. | 02-25-2010 |
20100099232 | Methods Of Forming Capacitors, And Methods Of Utilizing Silicon Dioxide-Containing Masking Structures - Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water. | 04-22-2010 |
20100133661 | METHODS FOR FORMING CONDUCTIVE VIAS IN SEMICONDUCTOR DEVICE COMPONENTS - A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole. | 06-03-2010 |
20100190314 | Methods Of Forming Semiconductor Structures - Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode. | 07-29-2010 |
20100193897 | SEMICONDUCTOR MATERIAL MANUFACTURE - Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed. | 08-05-2010 |
20100230724 | METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES, AND RELATED STRUCTURES - Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example. | 09-16-2010 |
20100244261 | THROUGH-HOLE CONTACTS IN A SEMICONDUCTOR DEVICE - Devices with conductive through-waver vias. In one embodiment, the device is formed by a method comprising providing a layer of semiconducting material, forming a layer of metal on a first side of the layer of semiconducting material, forming an opening in the layer of semiconducting material to thereby expose a portion of the layer of metal, the opening extending from at least a second side of the layer of semiconducting material to the layer of metal, and performing a deposition process to form a conductive contact in the opening using the exposed portion of the metal layer as a seed layer. | 09-30-2010 |
20100276656 | Devices Comprising Carbon Nanotubes, And Methods Of Forming Devices Comprising Carbon Nanotubes - Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. | 11-04-2010 |
20100295148 | METHODS OF UNIFORMLY REMOVING SILICON OXIDE AND AN INTERMEDIATE SEMICONDUCTOR DEVICE - A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one density or strain therein. The silicon oxide having at least one cavity or more than one density or strain is exposed to a gaseous mixture of NH | 11-25-2010 |
20100301462 | METHOD AND APPARATUS PROVIDING AIR-GAP INSULATION BETWEEN ADJACENT CONDUCTORS USING NANOPARTICLES - A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap. | 12-02-2010 |
20100313907 | Method and Apparatus for Contamination Removal Using Magnetic Particles - Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from the surface of the substrate. | 12-16-2010 |
20110048475 | MEGASONIC CLEANING WITH CONTROLLED BOUNDARY LAYER THICKNESS AND ASSOCIATED SYSTEMS AND METHODS - Megasonic cleaning systems and methods of using megasonic pressure waves to impart cavitation energy proximate a surface of a microelectronic substrate are disclosed herein. In one embodiment, a megasonic cleaning system includes a process tank for containing a liquid, a support element for carrying a substrate submerged in the liquid, and first and second transducers positioned in the tank. The first transducer is further positioned and/or operated to initiate cavitation events in a bulk portion of the liquid proximate a surface of the substrate. The second transducer is further positioned and/or operated to control an interface of fluid friction between the substrate and the bulk portion of the liquid. | 03-03-2011 |
20110111597 | Methods of Utilizing Silicon Dioxide-Containing Masking Structures - Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water. | 05-12-2011 |
20110143543 | Method of Forming Capacitors, and Methods of Utilizing Silicon Dioxide-Containing Masking Structures - Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water. | 06-16-2011 |
20110149656 | MULTI-CELL VERTICAL MEMORY NODES - Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM. | 06-23-2011 |
20110159688 | Selective Metal Deposition Over Dielectric Layers - Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over the substrate layer. | 06-30-2011 |
20110193190 | SEMICONDUCTOR MATERIAL MANUFACTURE - Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed. | 08-11-2011 |
20110195547 | METHODS FOR FORMING INTERCONNECT STRUCTURES FOR INTEGRATION OF MULTI LAYERED INTEGRATED CIRCUIT DEVICES - Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed. | 08-11-2011 |
20110201211 | Method and Apparatus Providing Air-Gap Insulation Between Adjacent Conductors Using Nanoparticles - A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap. | 08-18-2011 |
20110203940 | Method of Selectively Removing Conductive Material - An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with the surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate. | 08-25-2011 |
20110212260 | Methods Of Forming Electrically Conductive Structures - Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings. | 09-01-2011 |
20110262710 | Rheological Fluids for Particle Removal - Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided. | 10-27-2011 |
20110272754 | MEMORIES AND THEIR FORMATION - Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array. | 11-10-2011 |
20120002477 | MEMORIES AND THEIR FORMATION - Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the first and second vertical levels, and a second data line over the first data line is selectively coupled to the second memory cells at the first and second vertical levels. | 01-05-2012 |
20120156871 | METHODS FOR FORMING CONDUCTIVE VIAS IN SEMICONDUCTOR DEVICE COMPONENTS - A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole. | 06-21-2012 |
20120174943 | MEGASONIC CLEANING WITH CONTROLLED BOUNDARY LAYER THICKNESS AND ASSOCIATED SYSTEMS AND METHODS - Megasonic cleaning systems and methods of using megasonic pressure waves to impart cavitation energy proximate a surface of a microelectronic substrate are disclosed herein. In one embodiment, a megasonic cleaning system includes a process tank for containing a liquid, a support element for carrying a substrate submerged in the liquid, and first and second transducers positioned in the tank. The first transducer is further positioned and/or operated to initiate cavitation events in a bulk portion of the liquid proximate a surface of the substrate. The second transducer is further positioned and/or operated to control an interface of fluid friction between the substrate and the bulk portion of the liquid. | 07-12-2012 |
20120187335 | WET ETCHANTS INCLUDING AT LEAST ONE ETCH BLOCKER - Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed. | 07-26-2012 |
20120199987 | METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES, AND RELATED STRUCTURES - Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example. | 08-09-2012 |
20120220126 | Selective Metal Deposition Over Dielectric Layers - Selective deposition of metal over dielectric layers in a manner that minimizes of eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured as allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer. | 08-30-2012 |
20120235106 | METHODS OF FORMING AT LEAST ONE CONDUCTIVE ELEMENT, METHODS OF FORMING A SEMICONDUCTOR STRUCTURE, METHODS OF FORMING A MEMORY CELL AND RELATED SEMICONDUCTOR STRUCTURES - Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed. | 09-20-2012 |
20120261627 | Compositions of Matter, and Methods of Removing Silicon Dioxide - Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX | 10-18-2012 |
20120298158 | MICROELECTRONIC SUBSTRATE CLEANING SYSTEMS WITH POLYELECTROLYTE AND ASSOCIATED METHODS - Several embodiments of cleaning systems using polyelectrolyte and various associated methods for cleaning microelectronic substrates are disclosed herein. One embodiment is directed to a system that has a substrate support for holding the microelectronic substrate, a dispenser positioned above the substrate support and facing a surface of the microelectronic substrate, a reservoir in fluid communication with the dispenser via a conduit, and a washing solution contained in the reservoir. The washing solution includes a polyelectrolyte. | 11-29-2012 |
20120326221 | MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described. | 12-27-2012 |
20130000669 | RHEOLOGICAL FLUIDS FOR PARTICLE REMOVAL - Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided. | 01-03-2013 |
20130003303 | MICROELECTRONIC DEVICES WITH IMPROVED HEAT DISSIPATION AND METHODS FOR COOLING MICROELECTRONIC DEVICES - Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices. | 01-03-2013 |
20130005143 | METHOD AND APPARATUS PROVIDING AIR-GAP INSULATION BETWEEN ADJACENT CONDUCTORS USING NANOPARTICLES - A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap. | 01-03-2013 |
20130014696 | APPARATUS TO CONDUCT SPIN-ON FILM PROCESSING - An apparatus and process operate to impose acoustic radiation pressure upon a spin-on mass to alter topography of the spin-on mass. Other apparatus and processes are disclosed. | 01-17-2013 |
20130084699 | Selective Metal Deposition Over Dielectric Layers - Selective deposition of metal over dielectric layers in a manner that minimizes of eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured as allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer. | 04-04-2013 |
20130175662 | SEMICONDUCTOR MATERIAL MANUFACTURE - Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed. | 07-11-2013 |
20130320291 | SEMICONDUCTOR STRUCTURES AND MEMORY CELLS INCLUDING CONDUCTIVE MATERIAL AND METHODS OF FABRICATION - Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed. | 12-05-2013 |
20140004256 | Methods of Forming Charge-Trapping Regions | 01-02-2014 |
20140037527 | Compositions of Matter, and Methods of Removing Silicon Dioxide - Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX | 02-06-2014 |
20140102903 | APPARATUS FOR PARTICLE REMOVAL - Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from a surface of the substrate are provided. | 04-17-2014 |
20140175653 | SEMICONDUCTOR DEVICES COMPRISING INTERCONNECT STRUCTURES AND METHODS OF FABRICATION - Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. | 06-26-2014 |
20140246716 | MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described. | 09-04-2014 |
20140248769 | Methods of Processing Substrates and Methods of Forming Conductive Connections to Substrates - Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material. | 09-04-2014 |
20140256098 | MEMORIES WITH MEMORY ARRAYS EXTENDING IN OPPOSITE DIRECTIONS FROM A SEMICONDUCTOR AND THEIR FORMATION - Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array. | 09-11-2014 |
20140322890 | POLISHING SYSTEMS AND METHODS FOR REMOVING CONDUCTIVE MATERIAL FROM MICROELECTRONIC SUBSTRATES - Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material. | 10-30-2014 |
20140373880 | APPARATUS FOR CONTAMINATION REMOVAL USING MAGNETIC PARTICLES - Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from a surface of the substrate. | 12-25-2014 |