Patent application number | Description | Published |
20110248700 | DEVICE AND METHOD FOR DETECTING A SUBSTANCE USING A THIN FILM RESONATOR (FBAR) HAVING AN INSULATING LAYER - A device for detecting at least one substance of a fluid, has a piezoacoustic thin film resonator with a piezoelectric layer on which electrode layers are arranged, and an adsorption surface for adsorbing the fluid substance, wherein the piezoelectric and electrode layers and the adsorption surface are designed and arranged on each other such that by electrically activating the electrode layers, an excitation alternating field can be coupled into the piezoelectric layer. The thin film resonator can be excited to a resonance oscillation frequency f | 10-13-2011 |
20120164716 | BIOCHIP SENSOR - Small and extremely small molecules and ions or atoms may be detected with the novel device with exceptional sensitivity. The detection is implemented in a simple manner by the known acoustic resonator FBAR or by means of other technologies that measure the physical properties of the filled layer. The permeability of substances (e.g. active ingredients) through membranes such as cell membranes, lipid bilayers, and cell walls can be examined by combining a sensor with the reservoir and the membrane. | 06-28-2012 |
20120184051 | DEVICE AND METHOD FOR DETECTING AT LEAST ONE SUBSTANCE - A device for detecting at least one substance may include a resonator which, on its surface facing away from the carrier, is provided with a chemically sensitive layer for selectively binding a substance that is to be detected. An acoustic mirror is arranged between the carrier and the resonator. The acoustic mirror constitutes a band elimination filter having two closely adjacent notch frequencies, as a result of which the device is capable of oscillating in two resonant frequencies. The mass binding of the substance and the temperature can be determined computationally from the measured resonant frequencies. | 07-19-2012 |
20120227474 | DEVICE COMPRISING A RESONATOR FOR DETECTING AT LEAST ONE SUBSTANCE OF A FLUID, METHOD FOR PRODUCING SAID DEVICE AND METHOD FOR DETECTING AT LEAST ONE SUBSTANCE OF ANOTHER FLUID - A device for detecting a substance of a fluid or the concentration of a substance of a fluid may include a carrier to which a resonator is applied, to which a chemically sensitive material for adsorption of a substance to be detected is applied. The adsorption of the substance increases the mass of the resonator. The concentration of the substance in the liquid can be determined by measuring the frequency change of the resonator. | 09-13-2012 |
Patent application number | Description | Published |
20100065891 | Compact Memory Arrays - Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels. | 03-18-2010 |
20100103722 | METHOD OF PROGRAMMING RESISTIVITY CHANGING MEMORY - A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing the resistance value to a threshold value, selecting, based on the comparison, a cell reset process to be employed for programming the at least one resistivity-changing memory cell to the high-resistance state. The selecting includes selecting a predetermined reset process as the cell reset process when the resistance value is less than the threshold value, and adjusting the predetermined process and selecting the adjusted predetermined reset process as the cell reset process when the resistance value is at least equal to the threshold value. | 04-29-2010 |
20100271855 | MEMORY CELL ARRANGEMENTS - In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line. | 10-28-2010 |
20110310674 | System and Method for Bit-Line Control - In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor. | 12-22-2011 |
20120155189 | System and Method for Level Shifter - In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component. | 06-21-2012 |
20130099289 | Compact Memory Arrays - Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels. | 04-25-2013 |
20140124827 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor. | 05-08-2014 |
Patent application number | Description | Published |
20100202218 | System and Method for Level Shifter - In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component. | 08-12-2010 |
20100214851 | System and Method for Bit-Line Control - In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor. | 08-26-2010 |
20100244791 | System and Method for Regulating a Power Supply - In an embodiment, a method for controlling an output voltage of a power supply system is disclosed. The method includes regulating the power supply to a first voltage. After regulating the power supply to a first voltage, the power supply is regulated to a second voltage, which includes changing an input to the power supply system, and altering charge at an output of the power supply system until the output voltage reaches the second output voltage. | 09-30-2010 |
20110194364 | NVM OVERLAPPING WRITE METHOD - The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time. | 08-11-2011 |
20110228611 | System and Method for Bit-Line Control - In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The bit-line driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor. | 09-22-2011 |
Patent application number | Description | Published |
20110069528 | ELECTRONIC DEVICE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND A METHOD FOR BLOCKING A DEVICE - One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state. | 03-24-2011 |
20110254589 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements. | 10-20-2011 |
20120170386 | Hybrid Read Scheme for Multi-Level Data - Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal S | 07-05-2012 |
20120176833 | ELECTRONIC DEVICE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND A METHOD FOR BLOCKING A DEVICE - One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state. | 07-12-2012 |
20120300566 | CURRENT SENSE AMPLIFIER WITH REPLICA BIAS SCHEME - Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance. | 11-29-2012 |
20130028026 | Memory and Method for Programming Memory Cells - A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element. | 01-31-2013 |
20130176053 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. | 07-11-2013 |
20140052896 | SYSTEM AND METHOD FOR EMULATING AN EEPROM IN A NON-VOLATILE MEMORY DEVICE - The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data. | 02-20-2014 |
20140133250 | CURRENT SENSE AMPLIFIER WITH REPLICA BIAS SCHEME - Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance. | 05-15-2014 |
20140146618 | CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT - A circuit arrangement, having a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and at least one second access line; an access controller configured to control an access to at least one electronic component of the plurality of electronic components via the at least one first access line and the at least one second access line; a bias circuit configured to provide a defined potential to at least one of the first access lines, wherein the bias circuit is configured, during an access to an electronic component via one selected first access line of the plurality of first access lines, to provide the defined potential to one or two first access lines of the plurality of first access lines, wherein the one or two first access lines are arranged adjacent to the selected first access line, and, wherein during the access to the electronic component, the potentials of the first access lines of the plurality of first access lines other than the selected first access line and the one or two first access lines arranged adjacent to the selected first access line are floating. | 05-29-2014 |
20140153348 | Operation Scheme for Non-Volatile Memory - A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted. | 06-05-2014 |
20140198583 | Method and System for Reducing the Size of Nonvolatile Memories - Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation. | 07-17-2014 |
20140241055 | Method and System for Reducing the Complexity of Electronically Programmable Nonvolatile Memory - Embodiments relate to memory devices and methods for firmly programming at least a portion of a plurality of electronically programmable and erasable nonvolatile memory cells in a processing of the nonvolatile memory devices. | 08-28-2014 |
20150039805 | System and Method to Emulate an Electrically Erasable Programmable Read-Only Memory - The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment. | 02-05-2015 |
20150049560 | Circuit Arrangement and Method for Operating a Circuit Arrangement - A circuit arrangement comprising a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and second access lines, the second access lines comprising at least two bit-lines; an access controller controlling access to at least one of the electronic components via the at least one first access line and the second access lines; and a first group of switches, wherein each switch comprises at least one control terminal and at least two controlled terminals. Each switch of the first group is connected to one of the at least two bit-lines via its control terminal and in a path between one first access line and a sense amplifier via its controlled terminals, and adjacent switches are connected via their control terminals to different bit-lines of the at least two bit-lines. | 02-19-2015 |
20150052387 | SYSTEMS AND METHODS UTILIZING A FLEXIBLE READ REFERENCE FOR A DYNAMIC READ WINDOW - A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts. | 02-19-2015 |
20150179270 | Method and System for Reducing the Size of Nonvolatile Memories - Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation. | 06-25-2015 |