Patent application number | Description | Published |
20080250252 | Systems and methods for bios processing - Methods and systems for Basic Input/Output System BIOS processing such as hashing are disclosed. In one embodiment, there is a direct interface between a security module and a non-volatile memory storing the BIOS in a computing system so that the security module may directly access the BIOS without using the central processing unit CPU as an intermediary. In one embodiment, the security module is powered by standby power and therefore can begin BIOS processing even if the computing system has not yet been turned on. | 10-09-2008 |
20090043916 | Handshake Free Sharing in a Computer Architecture - A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit. | 02-12-2009 |
20090045822 | Capacitive detection systems, modules and methods - Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area. | 02-19-2009 |
20090045823 | Power efficient capacitive detection - Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area. | 02-19-2009 |
20090046827 | Time interval measurement for capacitive detection - Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area. | 02-19-2009 |
20100011130 | Non-intrusive debug port interface - A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard. | 01-14-2010 |
20100176891 | SINGLE-PIN RC OSCILLATOR - Apparatus includes a single-pin input interface, which is operative to sense a voltage across a capacitor of a Resistor-Capacitor (RC) network in which the capacitor is repetitively charging and discharging so that the voltage oscillates as a function of time. A measurement circuit is coupled to measure time durations in which the capacitor is charging and in which the sensed voltage lies between first and second predefined thresholds. A clock generation circuit is coupled to generate an output clock signal having a frequency, and to adjust the frequency responsively to the measured time durations. | 07-15-2010 |
20100302198 | Power Efficient Capacitive Detection - Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area. | 12-02-2010 |
20100324841 | Capacitive Detection Systems, Modules and Methods - Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area. | 12-23-2010 |
20110007019 | SYSTEMS AND METHODS FOR USING TFT-BASED LCD PANELS AS CAPACITIVE TOUCH SENSORS - A display screen system operative in the presence of backlight, which may be provided by a rear light source or by a mirror according to reflective LCD technologies, to identify presence of a conductive member such as a finger, the system comprising a structural, transparent planar element including an array of structural, planar conductive areas independently electrically addressable by a source of electric power, each conductive area having a plurality of transparency states controlled by said source of electric power; and capacitance sensing circuitry operative to sense capacitance of at least one of said conductive areas. | 01-13-2011 |
20120150467 | POWER EFFICIENT CAPACITIVE DETECTION - Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area. | 06-14-2012 |
20120239848 | MITIGATION OF EMBEDDED CONTROLLER STARVATION IN REAL-TIME SHARED SPI FLASH ARCHITECTURE - An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met. | 09-20-2012 |
20130073810 | Memory Sharing Between Embedded Controller and Central Processing Unit Chipset - An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals. | 03-21-2013 |
20150089223 | PROTECTING MEMORY INTERFACE - An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits. | 03-26-2015 |
20150089234 | SECURE MEMORY INTERFACE WITH CUMULATIVE AUTHENTICATION - A method includes generating a first sequence of data words for sending over an interface. A second sequence of signatures is computed and interleaved into the first sequence, so as to produce an interleaved sequence in which each given signature cumulatively signs the data words that are signed by a previous signature in the interleaved sequence and the data words located between the previous signature and the given signature. The interleaved sequence is transmitted over the interface. | 03-26-2015 |