Patent application number | Description | Published |
20090030663 | SYSTEM AND METHOD FOR MODELING STOCHASTIC BEHAVIOR OF A SYSTEM OF N SIMILAR STATISTICAL VARIABLES - A system and method for modeling stochastic behavior of a system of N similar statistical variables using N uncorrelated/independent random model parameters. More particularly, a system and method of modeling device across chip variations and device mismatch. The method includes modeling stochastic behavior of a system of N similar statistical variables using N uncorrelated/independent random model parameters. The method includes providing a system of N similar statistical variables, wherein each stochastic variable has a same standard deviation. The method further includes partially correlating each and every pair of stochastic variables among N variables, wherein a degree of partial correlation is a same for all pairs of variables. A statistical model is constructed to represent a system of N stochastic variables in which only N independent stochastic model parameters are used. A one-to-one mapping relation exists between N model parameters and the N variables. The method further includes finding unique values of the N model parameters given a set of values of the N variables. Reversely, the method also includes finding the values of the N variables given a set of values of the N model parameters. | 01-29-2009 |
20090204365 | MODELING SPATIAL CORRELATIONS - Modeling spatial correlations of semiconductor characteristic variations is disclosed. In one embodiment, a method includes developing a solution for each of a plurality of specific forms of spatial correlations of a characteristic of a circuit design and developing a plurality of solution methods for a given spatial correlation; selecting one of the solutions that is closest to a desired spatial correlation; and modeling the desired spatial correlation using the selected solution. | 08-13-2009 |
20110093242 | Method and System for Constructing Corner Models for Multiple Performance Targets - A method, system and article of manufacture are disclosed for constructing corner models for multiple performance targets for circuit simulations. The method includes identifying N (N≧2) device and/or circuit performance targets F | 04-21-2011 |
20110213587 | METHOD AND COMPUTER PROGRAM PRODUCT FOR FINDING STATISTICAL BOUNDS, CORRESPONDING PARAMETER CORNERS, AND A PROBABILITY DENSITY FUNCTION OF A PERFORMANCE TARGET FOR A CIRCUIT - Disclosed are embodiments of a method and an associated computer program product for finding the statistical bounds, the corresponding parameter corners and the probability density function of one or more performance targets for a circuit without requiring Monte Carlo simulation runs. To accomplish this, a joint probability density function for independent parameters that affect the performance target can be constructed. Then, based on the joint probability density function, the statistical bounds of the performance target can be found by constructing an equal-probability-density surface of the joint probability density function and solving a constrained optimization problem on that equal-probability-density surface. Once the statistical bounds are determined, the corresponding parameter corners for the performance target can also be determined. After obtaining multiple statistical bounds corresponding to different accumulated probability density, the probability density function of the performance target can also be obtained. | 09-01-2011 |
20120035892 | METHOD AND SYSTEM OF DEVELOPING CORNER MODELS FOR VARIOUS CLASSES ON NONLINEAR SYSTEMS - A method, system and article of manufacture are disclosed for developing corner models for various classes of nonlinear systems. The method comprises the steps of determining whether an explicit relationship between one or more performance targets vs. statistical model parameters is known; and deciding, when an explicit relationship between one or more performance targets vs. statistical model parameters is known, whether the relationship is linear or nonlinear. The relationship is constructed in the fractional form when an explicit relationship between one or more performance targets vs. statistical model parameters is not known. In one embodiment, the invention provides an optimal corner model solution for a single performance target, which varies with statistical parameters nonlinearly. In another embodiment, the invention provides an optimal and common corner model solution for multiple performance targets which vary with statistical model parameters nonlinearly. A step of decreasing the order of a target function on statistical model parameters may be used in the process of generating corner models. | 02-09-2012 |
20120124530 | MAKING A DISCRETE SPATIAL CORRELATION CONTINUOUS - A mechanism is provided for making a discrete spatial correlation on a 2D grid continuous. The region has given grid points and each of the grid points has its discrete stochastic variable. Additional grid points and associated stochastic variables are established on the boundary and corners of the region. All correlation coefficients are obtained among the given discrete stochastic variables and the additional discrete stochastic variables. For each of two given spatial points whose spatial correlation is needed, a quadrilateral containing it is identified by four grid points, and a stochastic variable for it is expressed as a weighted linear combination of four stochastic variables at four grid points, with four weights being a continuous function of the coordinate of the point. The resulting spatial correlation is a weighted linear combination of multiple discrete correlation coefficients each weight being a continuous function of the coordinates of the two given points. | 05-17-2012 |
20120126792 | STRUCTURES AND METHODS FOR RF DE-EMBEDDING - Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures. | 05-24-2012 |
20120212877 | CAPACITOR STRUCTURE - The disclosure relates generally to capacitor structures and more particularly, to capacitor structures having interdigitated metal fingers. Metal finger capacitors may have at least one layer, the at least one layer including: a first set of fingers, wherein each finger of the first set includes an end integrally connected to a bus segment of a first bus; a second set of fingers interdigitated with the first set of fingers, wherein each finger of the second set includes an end integrally connected to a bus segment of a second bus; an in port integrally connected to the first bus and an out port integrally connected to the second bus; and wherein a width of the first and second bus is non-uniform across a length of the first and second bus. | 08-23-2012 |
20120226456 | METHOD OF CALCULATING FET GATE RESISTANCE - A method and device determine FET gate resistance based on both polysilicon resistance and the resistance values of wires and contacts connected to the gate node, plus the fraction of the electric current in each wire segment and in each contact and the path length of electric current in polysilicon. A new gate resistance expression (i.e., a master equation) is used for total gate resistance, which is the sum of core gate resistance and the resistance of wires and contacts connecting polysilicon and a gate node. When there are two or more paths for electric current going from polysilicon to the gate node, the total resistance also depends on the direction and path length of electric current in polysilicon, and the method and device next determine the fraction of electric current in each path by minimizing total resistance with respect to the fractions of the electric current in each path. | 09-06-2012 |
20120227020 | METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS - A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device. | 09-06-2012 |
20120254820 | METHOD, A PROGRAM STORAGE DEVICE AND A COMPUTER SYSTEM FOR MODELING THE TOTAL CONTACT RESISTANCE OF A SEMICONDUCTOR DEVICE HAVING A MULTI-FINGER GATE STRUCTURE - Disclosed are embodiments for modeling contact resistance of devices, such as metal oxide semiconductor field effect transistors or varactors, that specifically have a multi-finger gate structure. In the embodiments, a set of expressions for total contact resistance are presented, in which (i) the total contact resistance is the sum of the resistance contribution from the contact (or the set of all contacts) in each diffusion region, (ii) the resistance contribution from the contact (or the set of all contacts) to the total contact resistance is the product of its resistance and the square of the relative electric current passing through it, and (iii) the electric current passing through the contact (or the set of all contacts) in a shared diffusion region (i.e., in an inner diffusion region) is twice of the electric current passing through the contact (or the set of all contacts) in an unshared diffusion region (i.e., in an outer diffusion region). | 10-04-2012 |
20120311518 | METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION - Disclosed are embodiments of a method and program storage device for modeling the resistance of a multi-contacted diffusion region of a semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET), a metal oxide semiconductor capacitor (MOS capacitor), a bipolar transistor, etc. The embodiments provide a formula for determining the total parasitic resistance (R | 12-06-2012 |
20120326270 | INTERDIGITATED VERTICAL NATIVE CAPACITOR - A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure. | 12-27-2012 |
20130007686 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR MODELING THE CAPACITANCE ASSOCIATED WITH A DIFFUSION REGION OF A SILICON-ON-INSULATOR DEVICE - Disclosed are embodiments of a method, system and program storage device for accurately modeling parasitic capacitance(s) associated with a diffusion region of a silicon-on-insulator (SOI) device and doing so based, at least in part, on proximity to adjacent conductive structures. In these embodiments, the layout of an integrated circuit design can be analyzed to determine, for the diffusion region, shape, dimension and proximity information. Then, a formula can be developed and used for determining the parasitic capacitance between the diffusion region and the substrate below (C | 01-03-2013 |
20130024828 | SOLUTIONS FOR NETLIST REDUCTION FOR MULTI-FINGER DEVICES - A computer-implemented method for performing a layout extraction for a multi-fingered semiconductor device is disclosed. The method reduces the netlist for the device and the number of device fingers by identifying a set of device common nodes, and combining a plurality of parasitic elements in the device to form a set of representative parasitic elements which are connected to respective device common nodes. In one embodiment, the method includes: extracting a netlist for the multi-finger device which includes a plurality of parasitic elements identifying a set of common nodes; replacing the fingers of the multi-finger device with a new device having a width equivalent to the widths of the fingers of the multi-finger device; and combining the parasitic elements of at least one device common node into a single representative parasitic element which is representative of the original parasitic elements. | 01-24-2013 |
20130174109 | DEVICE MISMATCH CORNER MODEL - A device mismatch corner model for semiconductor device simulation is provided. A method of providing the device mismatch corner model for semiconductor device simulation, includes selecting a type of electric performance target F for a type of device, determining a number N of semiconductor devices for which mismatches among electric performance targets of the semiconductor devices are simulated, and determining a desired k-sigma mismatch corner value among N(N−1)/2 pairs of the electric performance targets. The method further includes identifying at least one electric parameter P of the semiconductor devices that has a mismatch component and contributes to the mismatches among the electric performance targets of the semiconductor devices, determining a plurality of corner values for the at least one electrical parameter P, and running at most N circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations. | 07-04-2013 |
20130179127 | METHOD OF MODELING SPATIAL CORRELATIONS AMONG INTEGRATED CIRCUITS WITH RANDOMLY GENERATED SPATIAL FREQUENCIES - A computer-implemented method, computer system, and computer program for modeling spatial correlations among a set of devices. A method includes: assigning a set of physical coordinates to each device in the set of devices; representing one of a process parameter or an electric parameter for each device as a sum of at least two stochastic terms, wherein the at least two stochastic terms are chosen to satisfy the spatial correlations; simulating formation of the set of devices using the physical coordinates and the at least one of the process parameter or the electric parameter; and obtaining statistical properties of the set of devices from the simulation. | 07-11-2013 |
20130289964 | MODELING THE TOTAL PARASITIC RESISTANCES OF THE SOURCE/DRAIN REGIONS OF A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR - In the embodiments, a full resistive network is used to determine resistance contributions to the total parasitic resistance of each source/drain region of a multi-fin multi-gate field effect transistor (MUGFET). These resistance contributions include: a first resistance contribution of end portions of the fins, which are connected in pseudo-parallel by a local interconnect; second resistance contributions of segments of the local interconnect, which are connected in pseudo-series; and any other resistance contributions of any other resistive elements between the end portions of the fins and a single resistive element through which all the diffusion region current flows. The multi-fin MUGFET is then represented in a netlist as a simple field effect transistor with the total parasitic resistances represented as single resistive elements connected to the source/drain nodes of that field effect transistor. This simplified netlist is then used to simulate performance of the multi-fin MUGFET. | 10-31-2013 |
20130297277 | MODELING GATE RESISTANCE OF A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR - The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element. | 11-07-2013 |
20140103434 | MULTI-FINGER TRANSISTOR LAYOUT FOR REDUCING CROSS-FINGER ELECTRIC VARIATIONS AND FOR FULLY UTILIZING AVAILABLE BREAKDOWN VOLTAGES - Structure and methods for a semiconductor transistor design. The transistor structure comprises a field effect transistor having a multi-finger gate and three or more diffusion regions. Each diffusion region is identified as either a source region or a drain region, and each diffusion region is further identified as either an inner diffusion region or an outer diffusion region. Electrical contacts are established in the inner diffusion regions and the outer diffusion regions. There are approximately twice as many contacts in an inner source region as in the outer source region. There are approximately twice as many contacts in an inner drain region as in the outer drain region. The number and locations of contacts in each diffusion region are adjusted to reduce the difference among source node voltages of all fingers and the difference among drain node voltages of all fingers. | 04-17-2014 |
20140117453 | LOCAL INTERCONNECTS FOR FIELD EFFECT TRANSISTOR DEVICES - A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device. | 05-01-2014 |
20150057980 | STRUCTURES AND METHODS FOR RF DE-EMBEDDING - Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures. | 02-26-2015 |
20150089464 | SYSTEM AND METHOD FOR GENERATING A FIELD EFFECT TRANSISTOR CORNER MODEL - Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value with all statistical model parameters set at their nominal values. Then, multiple additional simulation runs are performed to determine corner performance values. In each successive additional simulation run, statistical model parameters of the different types of field effect transistors are offset from their nominal model parameters values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined. | 03-26-2015 |