Patent application number | Description | Published |
20090304124 | REDUCED-COMPLEXITY MULTIPLE-INPUT, MULTIPLE-OUTPUT DETECTION - A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations. | 12-10-2009 |
20100042897 | SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS - In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values. | 02-18-2010 |
20100057977 | REDUCED-POWER PROGRAMMING OF MULTI-LEVEL CELL (MLC) MEMORY - In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log | 03-04-2010 |
20100107030 | LDPC DECODERS USING FIXED AND ADJUSTABLE PERMUTATORS - In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices. | 04-29-2010 |
20100131819 | LDPC DECODER VARIABLE NODE UNITS HAVING FEWER ADDER STAGES - In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and w | 05-27-2010 |
20100202082 | Systems and Methods for Variable Fly Height Measurement - Various embodiments of the present invention provide systems and methods for determining fly height. For example, a system for fly height determination is disclosed that includes a head assembly disposed in relation to a storage medium, a write channel, and a read circuit. The read circuit is operable to receive information from both the head assembly and the write channel. A frequency determination circuit is included that is operable to receive a first signal from the read circuit corresponding to information received from the write channel and to provide a first fundamental frequency and a first higher order frequency based on the first signal, and the frequency determination circuit is operable to receive a second signal from the read circuit corresponding to information received from the head assembly channel and to provide a second fundamental frequency and a second higher order frequency based on the second signal. A compensation variable calculation module is included that is operable to divide the first fundamental frequency by the first higher order harmonic to yield a compensation variable. A fly height calculation module is included that is operable to divide the second fundamental frequency by the second higher order harmonic and the compensation variable to yield an indication of a distance between the head assembly and the storage medium. | 08-12-2010 |
20100275088 | LOW-LATENCY DECODER - In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated. | 10-28-2010 |
20120087035 | Systems and Methods for Variable Compensated Fly Height Measurement - Various embodiments of the present invention provide systems and methods for determining fly height. | 04-12-2012 |
Patent application number | Description | Published |
20100185924 | Method and Apparatus for Evaluating Performance of a Read Channel - Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | 07-22-2010 |
20110119566 | Method and Apparatus for Evaluating Performance of a Read Channel - Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | 05-19-2011 |
20110191652 | MEMORY READ-CHANNEL WITH SELECTIVE TRANSMISSION OF ERROR CORRECTION DATA - A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data. | 08-04-2011 |
20110216586 | Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding - Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell. | 09-08-2011 |
20110246862 | HARD INPUT LOW DENSITY PARITY CHECK DECODER - A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated. The exemplary method terminates based on a predefined syndrome output. | 10-06-2011 |
20120030539 | ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION - Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing. | 02-02-2012 |
20120126903 | Stabilized Digital Quadrature Oscillator - A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively. | 05-24-2012 |
Patent application number | Description | Published |
20080258908 | Systems and Methods for Communications Activity Status - Various systems and methods for indicating the status of a communication are disclosed herein. For example, status indication methods are disclosed that include initiating a communication that allows for communication between two persons. Further, the methods include determining a combination of status. The combination of status is based on a determination of two or more of the following: a calendar status, a power status, an activity status, and a location status. A communication status message is updated based at least in part on the determined combination of status. | 10-23-2008 |
20080259479 | System and Methods for Copying Digital Information from a Digital Media - System and Methods for Copying Digital Information from a Digital Media Various embodiments of the present invention provide systems and methods for copying or ripping digital information contained on one media to another media. In particular, some embodiments of the present invention provide methods and systems for copying digital information contained in a first fixed media onto another media by using digital information content corresponding to that maintained on the first fixed media, but obtained from a database. | 10-23-2008 |
20100093393 | Systems and Methods for Music Recognition - Various systems and methods for music recognition are disclosed herein. For example, music recognition devices are disclosed that include a data receiver that is operable to receive a data signal incorporating an identification of a currently playing song. The devices further include a memory and a processor. The memory includes instructions executable by the processor to: parse the data signal and to cause the identification to be stored to the memory. At least a portion of the identification is maintained in the memory after the currently playing song has terminated. | 04-15-2010 |
Patent application number | Description | Published |
20080301527 | SYSTEMS AND METHODS FOR JOINT LDPC ENCODING AND DECODING - Various embodiments of the present invention provide systems and methods for LDPC encoding and decoding. For example, a system for performing LDPC encoding and decoding is disclosed that includes a joint LDPC encoder/decoder. The joint LDPC encoder/decoder includes both an LDPC decoder and an LDPC encoder that each utilize a common LDPC decoder circuit to perform the respective functions of encoding and decoding. | 12-04-2008 |
20090030901 | SYSTEMS AND METHODS FOR FAX BASED DIRECTED COMMUNICATIONS - Various embodiments of the present invention provide systems and methods for responding to business related queries. As one example, such methods may include providing a communication direction associated with a particular business, and receiving a query via the communication direction. The received query is directed to a third party support service where it is parsed and one or more elements of the query are compared against a prior query. A response to the query was previously supplied by the particular business. A response is provided to the query that includes at least a portion of the reply to the prior query. | 01-29-2009 |
20090109564 | Low-power read channel for magnetic mass storage systems - An improved mass storage system having a read channel adapted to store in a FIFO memory digitized analog samples of data symbols read from a disk, the buffered digitized samples being processed by digital circuitry that may be operated at a slower speed than the maximum symbol rate from the disk. In one embodiment, the read channel has an analog portion that processes analog signals from a read head and includes an ADC for converting the processed analog signals into digital samples in response to a first clock; a FIFO storing therein the digital samples in response to the first clock and reading out the stored digital samples in response to a second clock; and a detector, in response to the second clock, detecting the digital samples from the FIFO into digital data. The maximum frequency of the first clock is less than the maximum frequency of the second clock. | 04-30-2009 |
20090199071 | Systems and Methods for Low Cost LDPC Decoding - Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update. | 08-06-2009 |