Patent application number | Description | Published |
20090085630 | ARBITRARY CLOCK CIRCUIT AND APPLICATIONS THEREOF - A clock circuit includes a waveform generator, a comparison module, and a clock signal module. The waveform generator is coupled to generate a waveform based on a reference oscillation. The comparison module is coupled to compare the waveform with a plurality of references to produce a plurality of waveform comparisons. The clock signal module is coupled to generate a clock signal from the plurality of waveform comparisons. | 04-02-2009 |
20100040184 | METHOD AND SYSTEM FOR COEXISTENCE IN A MULTIBAND, MULTISTANDARD COMMUNICATION SYSTEM UTILIZING A PLURALITY OF PHASE LOCKED LOOPS - Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs. | 02-18-2010 |
20100048196 | METHOD AND SYSTEM FOR A VARIABLE SYSTEM ON DEMAND - Methods and systems for a variable system on demand are disclosed. Aspects of the method may include configuring one or more filters in a wireless transmitter and/or receiver for a desired band and standard. The presence of a blocker signal in a receiver may be known and/or determined and the receiver may be configured for mitigating the blocker signal. A desired received signal strength indicator may be compared to a wideband received signal strength indicator. Gain levels may be configured in the receiver based on the comparison. Linearity of the receiver may be configured for blocker signal mitigation. The filters may include baseband filters and/or may be at an output of the receiver. The filters may include a plurality of stages, with one or more of the stages bypassed for filter configuring, and may include a mixer as an input. Capacitors and/or resistors may be configured in the filters. | 02-25-2010 |
20120236766 | Method and System for Coexistence in a Multiband, Multistandard Communication System Utilizing a Plurality of Phase Locked Loops - Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs. | 09-20-2012 |
20130029613 | Method and System For Coexistence In A Multiband, Multistandard Communication System Utilizing A Plurality of Phase Locked Loops - Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the Plls to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCOMA, for example. The frequencies may be configured to mitigate interference. Plls may be shared when operating in TOO mode, and used separately operating in FOO mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for AOCs and/or DACs in the transceiver may be generated utilizing the PLLs. | 01-31-2013 |
20130113117 | Wireless Communication Devices With In-Package Integrated Passive Components - Embodiments of the present disclosure can be used to both reduce the size and cost and improve the performance and power consumption of next generation wireless communication devices. In particular, embodiments enable board and semiconductor substrate area savings by using the fabrication package (which encapsulates the semiconductor substrate) as a design element in the design of next generation wireless communication devices. Specifically, embodiments use the substrate of the fabrication package to integrate into it components of the wireless radio transceiver (which are conventionally integrated into the semiconductor substrate) and other discrete components of the communication device (which are conventionally placed on the board of the device). As such, reduced board and semiconductor area can be realized. | 05-09-2013 |
20130113535 | Apparatus and Method for Fast Phase Locked Loop (PLL) Settling for Cellular Time-Division Duplex (TDD) Communications Systems - A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation. | 05-09-2013 |
20130114171 | Apparatus for Electrostatic Discharge Protection and Noise Suppression in Circuits - An integrated circuit assembly is provided that includes an integrated circuit (IC) package substrate including a package ground rail that is divided into a plurality of segments that are electrically isolated from each other. An IC die is disposed on the IC package substrate, the IC die including a plurality of circuit blocks and an IC ground rail. The IC ground rail is divided into a plurality of segments, where each segment of the IC ground rail is coupled to another segment of the IC ground rail by one or more diodes. The plurality of circuit blocks have corresponding ground nodes electrically connected to corresponding segments of the IC ground rail. The segments of the IC ground rail are electrically coupled to corresponding segments of the package ground rail by corresponding first connections. | 05-09-2013 |
20130114469 | Power-Efficient Multi-Mode Transceiver Synthesizer Configurations - Embodiments of the present disclosure provide power-efficient time division duplexing (TDD) mode configurations of frequency division duplexing (FDD) transceivers. Embodiments avoid time slotted operation of the receive and transmit synthesizers, thereby avoiding undesired operation under transient conditions, frequent calibration, and reduced power supply efficiency. In embodiments, a single synthesizer is used to enable TDD operation, thereby reducing power consumption and calibration requirements by approximately 50%. The single synthesizer may be maintained ON at all times, thus allowing the power supply's switching regulator to operate with substantially constant load conditions. | 05-09-2013 |
20130114771 | Minimization of Spurs Generated from a Free Running Oscillator - Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include adjusting the free-running oscillator to prevent the oscillation frequency from drifting so that the spurs are eliminated. Performance data generated when the communications device engages a communications channel that is known not to generate spurs is compared to performance data generated when the communications device engages a desired communications channel. The free-running oscillator is adjusted until the two types of performance data are matched. Other methods include adjusting the dithering module of the PLL to prevent the oscillation frequency from drifting so that the spurs are eliminated. | 05-09-2013 |
20130115905 | Reference Oscillator Arbitration and Scheduling for Multiple Wireless Subsystems - Systems and methods are described for controlling a reference oscillator shared by multiple subsystems of a communications system and arbitrating usage of the reference oscillator among these subsystems. By changing the properties of the reference oscillator (e.g., by tuning the reference oscillator) according to the needs of particular subsystem(s), the communications system can configure the reference oscillator to meet the specification requirements of these particular subsystem(s) and can later reconfigure the reference oscillator to meet the needs of other subsystems. Further, the controller can configure the subsystems based on parameters that impact multiple subsystems (e.g., by implementing geographic awareness, spectrum occupation awareness, and availability of Assisted GPS (AGPS) functionality) to achieve further optimization of the communications system. | 05-09-2013 |
20130116004 | Method for Suppression of Spurs from a Free Running Oscillator in Frequency Division Duplex (FDD) and Time Division Duplex (TDD) Wireless Systems - Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD. | 05-09-2013 |