| Patent application number | Description | Published |
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| 20100085086 | Digital Frequency Detector - In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values. | 04-08-2010 |
| 20100090723 | Symmetric Phase Detector - In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases. | 04-15-2010 |
| 20100090733 | Generating Multiple Clock Phases - In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases. | 04-15-2010 |
| 20100091925 | Triple Loop Clock and Data Recovery (CDR) - In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream. | 04-15-2010 |
| 20100091927 | Clock and Data Recovery (CDR) Using Phase Interpolation - In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals. | 04-15-2010 |
| 20100104057 | Clock and Data Recovery with a Data Aligner - In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock. | 04-29-2010 |
| 20100241918 | CLOCK AND DATA RECOVERY FOR DIFFERENTIAL QUADRATURE PHASE SHIFT KEYING - In one embodiment, a method includes receiving a first input stream, generating a first clock, sampling the first input stream based on the first clock, detecting a first phase difference between the first input stream and the first clock to generate a clock-correction signal and a first select signal, and generating a first recovered stream based on the first select signal. The method may additionally include receiving a second input stream, generating a second clock, sampling the second input stream based on the second clock, detecting a second phase difference between the second input stream and the second clock to generate a clock-correction signal and a second select signal, and generating a second recovered stream based on the second select signal. The method may further include adjusting the clocks based on the first and second clock-correction signals and combining the first and second recovered data streams to generate an output. | 09-23-2010 |
| 20120019299 | Clock Signal Correction - In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle. | 01-26-2012 |
| 20120023380 | ALGORITHMIC MATCHING OF A DESKEW CHANNEL - In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits. | 01-26-2012 |
