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Nieh, TW
Chien-Ming Nieh, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110298694 | ELECTROLUMINESCENT DISPLAY PANEL AND PIXEL STRUCTURE THEREOF - An electroluminescent (EL) display panel includes a blue EL device, a red EL device, a green EL device, a first power line electrically connected to the blue EL device, a second power line electrically connected to the red EL device, and a third power line electrically connected to the green EL device. The first power line has a first width, the second power line has a second width, and the third power line has a third width, wherein the first width is larger than the second width and the first width is larger than the third width. | 12-08-2011 |
Chun-Feng Nieh, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080242039 | METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION - A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds. | 10-02-2008 |
| 20110042729 | METHOD FOR IMPROVING SELECTIVITY OF EPI PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 02-24-2011 |
Chun-Feng Nieh, Baoshan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20080293204 | Shallow junction formation and high dopant activation rate of MOS devices - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer. | 11-27-2008 |
| 20090273034 | Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition - A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain. | 11-05-2009 |
| 20110027955 | Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition - A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain. | 02-03-2011 |
| 20110212590 | HIGH TEMPERATURE IMPLANTATION METHOD FOR STRESSOR FORMATION - An integrated circuit device and method of fabricating the integrated circuit device is disclosed. According to one of the broader forms of the invention, a method involves providing a semiconductor substrate. A combination of a pre-amorphous implantation process, a high temperature carbon implantation process, and/or an annealing process are performed on the substrate to form a stressor region. | 09-01-2011 |
Chun-Feng Nieh, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110039390 | Reducing Local Mismatch of Devices Using Cryo-Implantation - A method of forming an integrated circuit includes providing a semiconductor wafer, and forming a metal-oxide-semiconductor (MOS) device. The step of forming the MOS device includes forming a gate stack on the semiconductor wafer, and performing a cryo-implantation to form an implantation region adjacent the gate stack at a wafer temperature lower than 0° C. The step of performing the cryo-implantation is selected from the group consisting essentially of implanting the semiconductor wafer to form a pre-amorphized implantation (PAI) region; implanting the semiconductor wafer to form a lightly-doped source/drain region; implanting the semiconductor wafer to form a pocket/halo region; implanting the semiconductor wafer to form a deep source/drain region, and combinations thereof | 02-17-2011 |
| 20110111571 | METHOD FOR OBTAINING QUALITY ULTRA-SHALLOW DOPED REGIONS AND DEVICE HAVING SAME - A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×10 | 05-12-2011 |
| 20110316079 | Shallow Junction Formation and High Dopant Activation Rate of MOS Devices - A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer. | 12-29-2011 |
Chun-Feng Nieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110212592 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack. | 09-01-2011 |
| 20110291201 | MULTI-STRAINED SOURCE/DRAIN STRUCTURES - The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor. | 12-01-2011 |
Chun-Wen Nieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120012903 | METHOD FOR MAKING A DISILICIDE - Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height. | 01-19-2012 |
Cuo-Yo Nieh, Longtan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20100136712 | COMPOUND AND METHOD FOR PRODUCING THE SAME - The invention provides a Ti doped lead barium zirconate dielectric material which could be applied to high frequency devices. The material comprises a compound with the chemical formula (Pb | 06-03-2010 |
Jen Fou Nieh, Shengang Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090235991 | DETERGENT RELEASING DEVICE FOR WATER TANK - A detergent releasing device for toilet water tank includes a case connected to inside of the water tank and a releasing unit is connected with the case. The releasing unit includes a guide member with a hollow central tube in which an operation rod is movably inserted. The central tube includes two slots located close to two ends thereof. The operation rod includes an annular space in which a fixed amount of detergent is stored via one of the slots. The operation rod is connected with a float member which moves the operation rod up and down within the central tube. The fixed amount of detergent released when flushing. | 09-24-2009 |
Ji-Shyang Nieh, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090281745 | Monitoring Plasma Induced Damage During Semiconductor Wafer Processes - A plasma damage detection test structure is disclosed. The plasma damage detection test structure includes a first antenna, a voltage source, a ground reference, a first transistor comprising a first source, a first gate, and a first drain. The plasma damage detection test structure further includes a second transistor comprising a second source, a second gate, and a second drain. The first gate is conductively coupled to said first antenna, said first drain and said second drain are conductively coupled to said voltage source, and said first source and said second source are conductively coupled to said ground reference. In various embodiments multiple antennas may be used. The antennas may be multiple configurations, such as a symmetric arrangement or asymmetric arrangement. In various embodiments, multiple transistors in parallel or cross-couple arrangements may be used. | 11-12-2009 |
Ji-Shyang Nieh, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090321871 | Chip Pad Resistant to Antenna Effect and Method - A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC. | 12-31-2009 |
San-Wei Nieh, Jumg-Ho City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100037079 | BUILT-IN SYSTEM POWER MANAGEMENT CIRCUIT AND MOTHERBOARD WITH THEREOF - The invention has disclosed a system power management circuit comprising: a printed circuit board and a hardware monitor. The printed circuit board includes at least a first power connector, a second power connector, and more than one detection circuits disposed thereon; wherein the first power connector is used for electrically connecting a power supply, the second power connector is used for electrically connecting a power connector of a motherboard, inputs of the detection circuits are electrically connected to the first power connector, respectively. The hardware monitor is electrically connected to outputs of the detection circuits, and used for converting electrical signals outputted from the outputs of the detection circuits into corresponding digital signals, as well as for transmitting the digital signals to the motherboard via a two-wire bus, the two-wire bus is bidirectional, and may be an I | 02-11-2010 |
Shin-Yu Nieh, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090130853 | METHOD FOR FABRICATING A DEEP TRENCH IN A SUBSTRATE - The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate. | 05-21-2009 |
| 20090283856 | METHOD FOR FABRICATING A SEMICONDUCTOR CAPACITPR DEVICE - A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer. | 11-19-2009 |
| 20090311878 | METHOD FOR DEPOSITING A DIELECTRIC MATERIAL - A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant. | 12-17-2009 |
| 20100006954 | TRANSISTOR DEVICE - A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor. | 01-14-2010 |
| 20100172065 | CAPACITOR STRUCTURE - A capacitor structure includes: a top electrode, a bottom electrode, a first capacitor dielectric layer positioned between the top electrode and the bottom electrode and a second capacitor dielectric layer positioned between the top electrode and the bottom electrode. The first capacitor dielectric layer is selected from the group consisting HfO | 07-08-2010 |
| 20100310790 | METHOD OF FORMING CARBON-CONTAINING LAYER - A method of forming a carbon-containing layer is provided. First, a substrate having a target layer thereon is provided. Next, a plasma containing C | 12-09-2010 |
Shin-Yu Nieh, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110147887 | STACK CAPACITOR OF MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates. | 06-23-2011 |
Tsai-Chiang Nieh, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110169106 | MICRO ELECTRONIC MECHANICAL SYSTEM STRUCTURE AND MANUFACTURING METHOD THEREOF - A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed. | 07-14-2011 |
Ya-Yu Nieh, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100182516 | COMPLEX IMAGE DISPLAY DEVICE - A complex image display device comprises a light source, an illumination optical module, a micro display module, at least one optical projection module, at least one image-light-path switch module, an image-light-path control unit, and at least one image display screen, wherein the light source provides a light beam, the illumination optical module receives and shapes the light beam, continuously the light beam is projected by the illumination optical module. The micro display module provides an image-to-be-displayed and the light beam is then modulated by the image to become at least an image-modulated light beam for displaying. Then, the optical projection module receives and magnifies the image-modulated light beam. Continuously, the image-light-path switch module receives the magnified image-modulated light beam and switches the light path of the light beam. The image display screen, thus, receives and displays the magnified image-modulated light beam, which is switched by the image-light-path switch module. | 07-22-2010 |
Ya-Yu Nieh, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080252853 | COLOR-MIXING LASER MODULE AND PROJECTORS USING THE SAME - A color-mixing laser module is disclosed, which is comprised of a laser unit capable of emitting red, blue and green laser beams; a beam combiner, for receiving and converging the laser beams emitted from the laser unit and then directing the converged laser light to illuminate on a light pattern adjusting unit; and the light pattern adjusting unit, capable of receiving the converged laser light from the beam combiner for adjusting the pattern of the same. | 10-16-2008 |
Yeu-Perng Nieh, Ta-Li City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090019973 | Socket assembly for quickly releasing object engaged with the socket - A socket assembly includes a socket having a mounting hole which includes a plurality of insides and yield recesses located alternatively between the insides. A control member is rotatably mounted to the socket and has a through hole, a plurality of stops extend inward from an inner periphery of the through hole. A polygonal object is engaged with the mounting hole of the socket and the stops of the control member are located on the path along which the polygonal object may drop from the socket. After the object is loosened and received in the socket, the control member is rotated an angle to remove the stops such that the path that the polygonal object may drop is clear and the object is easily take out from the socket. | 01-22-2009 |
| 20090211409 | SOCKET ASSEMBLY FOR QUICKLY RELEASING OBJECT ENGAGED WITH THE SOCKET - A socket assembly includes a socket having a mounting hole which includes a plurality of insides and yield recesses located alternatively between the insides. A control member is rotatably mounted to the socket and has a through hole, a plurality of stops extend inward from an inner periphery of the through hole. The stops are deformable when being applied with a force along the axis of the through hole. A polygonal object can be forced into the mounting hole by squeezing and bending the stops. After the object is loosened and received in the socket, the stops support the nut from dropping from the mounting hole. When the control member is rotated to off align the stops from the path that the corners of the polygonal object may drop, the object is easily take out from the socket. | 08-27-2009 |
| 20110024998 | QUICK RELEASE DEVICE FOR SLEEVE ASSEMBLY - A sleeve assembly includes a sleeve having a hexagonal hole and a rectangular hole in two ends thereof and a positioning hole is defined through a wall of the sleeve and communicates with the hexagonal hole. A control member is rotatably mounted to the sleeve and a bead is located between the control member and the sleeve. The bead is movably engaged with the positioning hole. The control member includes multiple first reception portions and second reception portions defined in an inner periphery thereof. The bead is completely received in one of the first reception portions or partially received in one of the second reception portions by rotating the control member. When the bead is completely received in one of the first reception portions, the object in the sleeve drops off from the sleeve. | 02-03-2011 |
Yu-Chan Nieh, Tu-Cheng TW
| Patent application number | Description | Published |
|---|---|---|
| 20120027009 | COMMUNICATION DEVICE AND METHOD THEREOF - A communication device electronically connects with a phone and includes a control unit, a relay, a public switched telephone network (PSTN) interface, a voice over Internet Protocol (VoIP) network interface, and a ring signal detector. The relay is electronically connected with the control unit. The PSTN interface and the VoIP interface are electronically connected with the relay. The ring signal detector is electronically connected with the control unit and the PSTN interface. The control unit controls the relay to connect the phone with the PSTN interface when the ring signal detector detects a PSTN ring signal. In one embodiment, the control unit controls the relay to connect the phone with the VoIP interface. | 02-02-2012 |