| Patent application number | Description | Published |
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| 20090327129 | SOCIAL NETWORK ENABLED GROUP GIFT CARD - A system and method that allows for a group of individuals to easily contribute to the same gift card is disclosed. The gift card can be a traditional physical card or an electronic card. In one embodiment, an account administrator establishes a group enabled gift card account for self-consumption or for a specified gift recipient. The administrator engages potential group gift card contributors through various electronic communication mechanisms who can then add funds to the account. The contribution period may remain open based on criteria supplied by the administrator. Once the account is closed, the collected amount is transferred to a designated gift card and sent to the recipient. | 12-31-2009 |
| 20100114733 | Party Payment System - Systems and methods are disclosed herein which that enable a first party, such as a child, to selected one or more items offered by an online retailer and to send a request to a second party, such as a parent or guardian, to request that the second party purchase the item or items for the first party. The systems and methods provide the second party with the ability to view requests received from the first party, to set limits on the number of requests and the amounts of the requests that the first party may make. The second party may also designate the parties to whom the first party may submit purchase requests. The child may also submit request to one or more non-parental contributors who may contribute money toward the purchase the one or more items for the child. | 05-06-2010 |
| 20120022969 | RELATED PARTY PAYMENT SYSTEM - Systems and methods are disclosed herein which that enable a first party, such as a child, to selected one or more items offered by an online retailer and to send a request to a second party, such as a parent or guardian, to request that the second party purchase the item or items for the first party. The systems and methods provide the second party with the ability to view requests received from the first party, to set limits on the number of requests and the amounts of the requests that the first party may make. The second party may also designate the parties to whom the first party may submit purchase requests. The child may also submit request to one or more non-parental contributors who may contribute money toward the purchase the one or more items for the child. | 01-26-2012 |
| Patent application number | Description | Published |
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| 20090128975 | Integrated Circuit Protected Against Short Circuits and Operating Errors Following the Passage on an Ionizing Radiation - An integrated circuit chip comprising a number of semiconductor components exhibiting parasitic components through which a short-circuit between the circuit supply voltage and ground could occur, wherein said semiconductor components are distributed in elementary blocks, each elementary block being independently connected, for its power supply, to the supply or ground lines of the main supply network of the integrated circuit by a current-limiting device capable of stopping a short-circuit starting in the considered block, and each block being sized so that logic errors occurring in this block are correctable by error-correction means. | 05-21-2009 |
| 20090259897 | Logic circuit protected against transient disturbances - The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit ( | 10-15-2009 |
| 20100275074 | RUNTIME PROGRAMMABLE BIST FOR TESTING A MULTI-PORT MEMORY DEVICE - One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence. | 10-28-2010 |
