Patent application number | Description | Published |
20090154247 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-18-2009 |
20090201736 | INCREASED NAND FLASH MEMORY READ THROUGHPUT - A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches. | 08-13-2009 |
20100124126 | ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE - In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful. | 05-20-2010 |
20100124132 | REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells. | 05-20-2010 |
20100124133 | REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. | 05-20-2010 |
20100142280 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-10-2010 |
20110122717 | REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column. | 05-26-2011 |
20110161591 | INCREASED NAND FLASH MEMORY READ THROUGHPUT - A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches. | 06-30-2011 |
20110170353 | ACCESS LINE DEPENDENT BIASING SCHEMES - The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array. | 07-14-2011 |
20110222353 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 09-15-2011 |
20120033504 | ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE - In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful. | 02-09-2012 |
20120221779 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 08-30-2012 |
20120221780 | INCREASED NAND FLASH MEMORY READ THROUGHPUT - A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches. | 08-30-2012 |
20120281480 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 11-08-2012 |
20130135935 | ACCESS LINE DEPENDENT BIASING SCHEMES - The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array. | 05-30-2013 |
20130250707 | REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES - An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block. | 09-26-2013 |
20140104956 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 04-17-2014 |
20140204693 | APPLYING A VOLTAGE-DELAY CORRECTION TO A NON-DEFECTIVE MEMORY BLOCK THAT REPLACES A DEFECTIVE MEMORY BLOCK BASED ON THE ACTUAL LOCATION OF THE NON-DEFECTIVE MEMORY BLOCK - In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block. | 07-24-2014 |
20150355849 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 12-10-2015 |
Patent application number | Description | Published |
20080251019 | SYSTEM AND METHOD FOR TRANSFERRING A SUBSTRATE INTO AND OUT OF A REDUCED VOLUME CHAMBER ACCOMMODATING MULTIPLE SUBSTRATES - The present invention comprises a system and method for transferring a substrate into and out of a chamber configured to accommodate multiple substrates. In one embodiment, the system comprises a chamber housing that includes a first substrate support tray and a second substrate support tray independently movable along a vertical axis, and a substrate conveyor movable into and out of the chamber housing. The first substrate support tray and the second substrate support tray are movable to a position where a portion of the second substrate support tray is received in the first substrate support tray. | 10-16-2008 |
20090195262 | IN-LINE ELECTRON BEAM TEST SYSTEM - A method and apparatus for testing a plurality of electronic devices formed on a large area substrate is described. In one embodiment, the apparatus performs a test on the substrate in one linear axis in at least one chamber that is slightly wider than a dimension of the substrate to be tested. Clean room space and process time is minimized due to the smaller dimensions and volume of the system. | 08-06-2009 |
20100098518 | IN/OUT DOOR FOR A VACUUM CHAMBER - A load lock chamber sized for a large area substrate is provided. The load lock chamber includes a housing comprising a door and a body having at least two sealable ports, a movable door associated with at least one of the sealable ports, and a door actuation assembly coupled between the door and the housing. The door actuation assembly further includes a pair of first actuators coupled to the door for moving the door in a first direction, and a pair of second actuators for moving the door in a second direction that is orthogonal to the first direction. | 04-22-2010 |
20100327162 | IN-LINE ELECTRON BEAM TEST SYSTEM - A method and apparatus for testing a plurality of electronic devices formed on a large area substrate is described. In one embodiment, the apparatus performs a test on the substrate in one linear axis in at least one chamber that is slightly wider than a dimension of the substrate to be tested. Clean room space and process time is minimized due to the smaller dimensions and volume of the system. | 12-30-2010 |
20120113559 | ELECTROSTATIC DISCHARGE PREVENTION FOR LARGE AREA SUBSTRATE PROCESSING SYSTEM - Embodiments of the invention relate to methods and apparatus for minimizing electrostatic discharge in processing and testing systems utilizing large area substrates in the production of flat panel displays, solar panels, and the like. In one embodiment, an apparatus is described. The apparatus includes a testing chamber, a substrate support disposed in the testing chamber, the substrate support having a substrate support surface, a structure disposed in the testing chamber, the structure having a length that spans a width of the substrate support surface, the structure being linearly movable relative to the substrate support, and a brush device having a plurality of conductive bristles coupled to the structure and spaced a distance away from the substrate support surface of the substrate support, the brush device electrically coupling the support surface to ground through the structure. | 05-10-2012 |
Patent application number | Description | Published |
20100111164 | Method and System for Data Management in a Video Decoder - A method and system for minimizing bus traffic in a video decoder is disclosed. A method and system for processing a portion of a reference picture includes designating the reference picture, selecting a display picture within the reference picture, transmitting a display picture size, and sending a display picture offset. A method and system for compressing IDCT coefficients corresponding to a macroblock, the macroblock having a plurality of blocks, includes locating each non-zero IDCT coefficient corresponding to one of the plurality of blocks, assigning an index to the non-zero IDCT coefficient, the index designating a location within the one of the plurality of blocks, packing the non-zero IDCT coefficient in little endian format, and specifying a terminator bit corresponding to the non-zero coefficient, the terminator bit indicating the end of all non-zero IDCT coefficients for the one of the plurality of blocks. A method and system for selectively controlling each hardware device within a video decoder includes obtaining a video stream, performing VLC decoding, encoding a plurality of instructions to control each hardware device within the video decoder, decoding each one of the plurality of instructions, and optionally performing an IDCT in response to each one of the plurality of instructions. | 05-06-2010 |
20140010313 | Method and System for Data Management in a Video Decoder - A method and system for minimizing bus traffic in a video decoder is disclosed. A method and system for processing a portion of a reference picture includes designating the reference picture, selecting a display picture within the reference picture, transmitting a display picture size, and sending a display picture offset. A method and system for compressing IDCT coefficients corresponding to a macroblock, the macroblock having a plurality of blocks, includes locating each non-zero IDCT coefficient corresponding to one of the plurality of blocks, assigning an index to the non-zero IDCT coefficient, the index designating a location within the one of the plurality of blocks, packing the non-zero IDCT coefficient in little endian format, and specifying a terminator bit corresponding to the non-zero coefficient, the terminator bit indicating the end of all non-zero IDCT coefficients for the one of the plurality of blocks. | 01-09-2014 |
Patent application number | Description | Published |
20120173505 | INVERSE SEARCH SYSTEMS AND METHODS - Inverse search systems and methods operate on identifiers of content items in a corpus such as the World Wide Web In an inverse search, the user submits a query that includes an identifier of a target content item in the corpus and receives information (metadata) about the target content item being returned to the user. Many types of metadata can be returned, including ratings or other metadata related to the target content item obtained from users, popularity data specific to the target content item, information about previously submitted forward search queries that led to the target content item being identified as a hit, and metadata extracted from the target content item. | 07-05-2012 |
20130179465 | INVERSE SEARCH SYSTEMS AND METHODS - Inverse search systems and methods operate on identifiers of content items in a corpus such as the World Wide Web In an inverse search, the user submits a query that includes an identifier of a target content item in the corpus and receives information (metadata) about the target content item being returned to the user. Many types of metadata can be returned, including ratings or other metadata related to the target content item obtained from users, popularity data specific to the target content item, information about previously submitted forward search queries that led to the target content item being identified as a hit, and metadata extracted from the target content item. | 07-11-2013 |
20140108387 | INVERSE SEARCH SYSTEMS AND METHODS - Inverse search systems and methods operate on identifiers of content items in a corpus such as the World Wide Web In an inverse search, the user submits a query that includes an identifier of a target content item in the corpus and receives information (metadata) about the target content item being returned to the user. Many types of metadata can be returned, including ratings or other metadata related to the target content item obtained from users, popularity data specific to the target content item, information about previously submitted forward search queries that led to the target content item being identified as a hit, and metadata extracted from the target content item. | 04-17-2014 |
Patent application number | Description | Published |
20100190353 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 07-29-2010 |
20100285237 | NANOLAYER DEPOSITION USING BIAS POWER TREATMENT - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, comprising introducing a first plurality of precursors to deposit a thin layer with the deposition process not self limiting, followed by introducing a second plurality of precursors for plasma treating the thin deposited layer. The plasma can be isotropic, anisotropic, or a combination of isotropic and anisotropic to optimize the effectiveness of the treatment of the thin deposited layers. | 11-11-2010 |
20120021138 | NANOLAYER DEPOSITION PROCESS FOR COMPOSITE FILMS - A NanoLayer Deposition (NLD) process for depositing composite films of tertiary, quaternary, pentanary, and hexary stoichiometric films is provided. The inventive deposition process is a cyclic process consisting of a sequence of thin film deposition and treatment steps to obtain a desired film stoichiometry. The deposition steps are not self-limiting as in atomic layer deposition. In one embodiment for depositing a compound oxide film, the deposition process comprises a first deposition, followed by a hydrogen-containing plasma treatment, a second deposition followed by a hydrogen-containing plasma treatment, and then a third deposition followed by a hydrogen-containing plasma and then an oxygen-containing plasma treatment to produce a stoichiometric quaternary film. The cyclic process is repeated until the desired overall film thickness is achieved. The inventive process is used to fabricate high k dielectric films, ferroelectric films, piezoelectric films, and other complex oxides. | 01-26-2012 |
20120123623 | Electric vehicles with extended range. - The present invention discloses electric vehicles and methods to operate such vehicles, comprising an electric drive capable of moving the vehicles, together with a non-battery operative feature to enhance the performance of the vehicle, such as extending the range or increasing the power. The non-electrical enhanced feature is independent and not integrated with the electric drive, to enable the return of the vehicle design to pure electrical power with minimum modification. | 05-17-2012 |
20120202353 | NANOLAYER DEPOSITION USING PLASMA TREATMENT - A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps. | 08-09-2012 |
20120258257 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, including introducing a first plurality of precursors to deposit a thin film and introducing a second plurality of precursors to modify the deposited thin film. The deposition using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film, including treatments such as modification of film composition and doping or removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 10-11-2012 |
20120289061 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, including introducing a first plurality of precursors to deposit a thin film and introducing a second plurality of precursors to modify the deposited thin film. The deposition using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film, including treatments such as modification of film composition and doping or removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 11-15-2012 |
20140360446 | Hybrid Vehicles with Radial Engines - A radial cam engine with an optimized cam configuration can provide improve performance over crankshaft internal combustion engines. The cam configuration can include a flat-top or flat bottom piston motion, multiple lobe cam configurations, matching piston force with torque/force ratio in combustion phase, asymmetry piston motions for improved power transfer during combustion phase, and/or offset piston and cam configurations. The radial cam engine can be used in vehicles, such as hybrid vehicles. | 12-11-2014 |
20150174824 | Systems and methods for 3D printing with multiple exchangeable printheads - A modular 3D printer system can include a base subsystem and multiple exchangeable components. The base subsystem can have a 3D motion module, a printhead module and a platform module. The multiple exchangeable components can include printheads having different configurations and functionalities, which can be exchangeably installed in the printhead module. The multiple exchangeable components can include platform supports having different configurations and functionalities, which can be exchangeably installed in the platform module. | 06-25-2015 |
20160040424 | Pre-fabricated structures and methods - Building structures can be fabricated at an offsite, and then assembled at the construction site. The building structures can include beams and wall panels having metal attachments. The beams and wall panels can be assembled by coupling the metal attachments, for example, by welding. | 02-11-2016 |
Patent application number | Description | Published |
20150293030 | Sensor Array for Verifying the Condition of an Electronic Device - A system and method for evaluating the cosmetic condition of a used electronic device, comprising directing one or more beams of light at the surface of the device and evaluating the amount of reflected light and the amount of scattered light off the surface of the device. The system and method can be used to evaluate the condition of the device or to confirm a user's manually entered evaluation of the device's condition. | 10-15-2015 |
20150294278 | System and Method for Recycling Electronics - A kiosk for recycling electronics, comprising security features that prompt it to reject stolen or possibly stolen devices. | 10-15-2015 |
20150294320 | Method for Determining if a Used Electronic Device Belongs to a User - A method for determining whether a used electronic device has theft-detection software turned on. Such a method may be used at a repurchase facility or an automated kiosk to reject devices that may be stolen. | 10-15-2015 |
20150309912 | Electronics Recycling Retail Desktop Verification Device - A verification device for evaluating a used electronic device brought in for resale, intended to be used to assist a retail clerk in a resale transaction, said verification device capable of performing a functional test of a device, performing a cosmetic test of a device, and calculating its resale value. | 10-29-2015 |
20150316450 | Functional Testing Device for Used Electronics - A device and method for evaluating the functionality of an electronic device are provided. The functionality of the device may be evaluated manually, semi-automatically, or automatically. | 11-05-2015 |
20150324761 | System and Method for Recycling Electronics While Complying with Secondhand Transaction Reporting Laws - A system and method for recycling used electronic devices in a kiosk or a desktop device while reporting the transaction to law enforcement in a manner required by the local jurisdiction for secondhand dealers. | 11-12-2015 |
20150324870 | Method of Remotely Determining the Condition of a Used Electronic Device - A method of remotely performing a functional diagnostic and a cosmetic evaluation of a used electronic device, using an app installed on the device itself, and of using the evaluation data to determine a resale value for the device. | 11-12-2015 |
20150324926 | System and Method of Analyzing Insurance Claims for Electronic Devices - A method of remotely performing a functional diagnostic and a cosmetic evaluation of a used electronic device, using an app installed on the device itself, and of using the evaluation data to determine a resale value for the device. | 11-12-2015 |
20150330910 | Cosmetic Evaluation Box for Used Electronics - A cosmetic testing device for electronic devices that uses the electronic device's own camera to take photographs of the electronic device in order to determine its cosmetic condition. | 11-19-2015 |
20160019685 | Method for Performing a Cosmetic Evaluation of a Used Electronic Device - A system and method for cosmetic evaluation of an electronic device, using the device's own camera or cameras to take photos of the device itself using a mirror or mirrors. | 01-21-2016 |
20160034265 | Method for Bulk App Loading on Mobile Devices - A method of quickly installing a set of apps on a used smartphone, activating them by a process that does not require the user to set up multiple accounts, and a method of financing the process. | 02-04-2016 |
Patent application number | Description | Published |
20100190353 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 07-29-2010 |
20100285237 | NANOLAYER DEPOSITION USING BIAS POWER TREATMENT - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, comprising introducing a first plurality of precursors to deposit a thin layer with the deposition process not self limiting, followed by introducing a second plurality of precursors for plasma treating the thin deposited layer. The plasma can be isotropic, anisotropic, or a combination of isotropic and anisotropic to optimize the effectiveness of the treatment of the thin deposited layers. | 11-11-2010 |
20120021138 | NANOLAYER DEPOSITION PROCESS FOR COMPOSITE FILMS - A NanoLayer Deposition (NLD) process for depositing composite films of tertiary, quaternary, pentanary, and hexary stoichiometric films is provided. The inventive deposition process is a cyclic process consisting of a sequence of thin film deposition and treatment steps to obtain a desired film stoichiometry. The deposition steps are not self-limiting as in atomic layer deposition. In one embodiment for depositing a compound oxide film, the deposition process comprises a first deposition, followed by a hydrogen-containing plasma treatment, a second deposition followed by a hydrogen-containing plasma treatment, and then a third deposition followed by a hydrogen-containing plasma and then an oxygen-containing plasma treatment to produce a stoichiometric quaternary film. The cyclic process is repeated until the desired overall film thickness is achieved. The inventive process is used to fabricate high k dielectric films, ferroelectric films, piezoelectric films, and other complex oxides. | 01-26-2012 |
20120202353 | NANOLAYER DEPOSITION USING PLASMA TREATMENT - A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps. | 08-09-2012 |
20120258257 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, including introducing a first plurality of precursors to deposit a thin film and introducing a second plurality of precursors to modify the deposited thin film. The deposition using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film, including treatments such as modification of film composition and doping or removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 10-11-2012 |
20120289061 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, including introducing a first plurality of precursors to deposit a thin film and introducing a second plurality of precursors to modify the deposited thin film. The deposition using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film, including treatments such as modification of film composition and doping or removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 11-15-2012 |
20140360446 | Hybrid Vehicles with Radial Engines - A radial cam engine with an optimized cam configuration can provide improve performance over crankshaft internal combustion engines. The cam configuration can include a flat-top or flat bottom piston motion, multiple lobe cam configurations, matching piston force with torque/force ratio in combustion phase, asymmetry piston motions for improved power transfer during combustion phase, and/or offset piston and cam configurations. The radial cam engine can be used in vehicles, such as hybrid vehicles. | 12-11-2014 |
20150174824 | Systems and methods for 3D printing with multiple exchangeable printheads - A modular 3D printer system can include a base subsystem and multiple exchangeable components. The base subsystem can have a 3D motion module, a printhead module and a platform module. The multiple exchangeable components can include printheads having different configurations and functionalities, which can be exchangeably installed in the printhead module. The multiple exchangeable components can include platform supports having different configurations and functionalities, which can be exchangeably installed in the platform module. | 06-25-2015 |
20160087141 | Composite substrates of silicon and ceramic - Composite substrates include a single crystal silicon layer disposed on a ceramic layer, including a transparent glass layer. Combination of single crystal devices and non-single crystal devices can be fabricated on a ceramic substrate. | 03-24-2016 |
20160089898 | Printing on liquid medium using liquid ink - Ink jet printing on a liquid medium can be performed using liquid inks having a thermo inversion gelling property. The liquid ink can include a hyperthermogelling component having a gelling temperature. When the liquid ink is jetted on the liquid medium, the liquid ink can gel to form gel dots. The gel dots can resist against liquid dispersion, allowing the formation of a high resolution image on the liquid medium. | 03-31-2016 |