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Nguyen, Fremont
An-Dien Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090059209 | LOCK-IN DEMODULATION TECHNIQUE FOR OPTICAL INTERROGATION OF A GRATING SENSOR - A grating sensor and method for optical interrogation of that sensor uses a lock-in technique to achieve simultaneous measurements of strain (and related temperature) and ultrasonic stress wave signals, as well as other environmental conditions that affect a reflection spectrum of the grating sensor. It achieves this by using a lock-in amplifier or a software demodulator to detect slight shifts in the grating reflection spectrum with high sensitivity and accuracy. A dynamic feedback loop based on the lock-in error signal output retunes the light wavelength of the light source (e.g., a tunable laser) or of a wavelength filter in the reflection path to maintain it relative to a specified reflection point of the grating reflector. The lock-in error signal serves as a measure of temperature/strain changes and of ultrasonic vibrations. | 03-05-2009 |
Dan Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100076452 | Systems, methods and devices for removing obstructions from a blood vessel - Devices and methods for removing an obstruction from a blood vessel are described. The devices are deployed in a collapsed condition and are then expanded within the body. The devices are then manipulated to engage and remove the obstruction. | 03-25-2010 |
Dzung Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100039864 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-18-2010 |
| 20100157683 | APPARATUS AND METHOD FOR REDUCED PEAK POWER CONSUMPTION DURING COMMON OPERATION OF MULTI-NAND FLASH MEMORY DEVICES - System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption. | 06-24-2010 |
| 20110032761 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-10-2011 |
Dzung H. Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090154247 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-18-2009 |
| 20090201736 | INCREASED NAND FLASH MEMORY READ THROUGHPUT - A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches. | 08-13-2009 |
| 20100124126 | ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE - In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful. | 05-20-2010 |
| 20100124132 | REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells. | 05-20-2010 |
| 20100124133 | REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. | 05-20-2010 |
| 20100142280 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-10-2010 |
| 20110122717 | REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column. | 05-26-2011 |
| 20110161591 | INCREASED NAND FLASH MEMORY READ THROUGHPUT - A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches. | 06-30-2011 |
| 20110170353 | ACCESS LINE DEPENDENT BIASING SCHEMES - The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array. | 07-14-2011 |
| 20110222353 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 09-15-2011 |
Han Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090210794 | User Customized Portable Desktop - The invention provides a portable customizable desktop environment, enabling a User to replicate and use the User's preferred desktop configuration on any computing device by means of an enabled portable memory device such as USB drive. Further, the portable desktop can be encapsulated, such that little if any trace of the use of the portable desktop are glean-able from the host computer. Also provided is a method of learning to duplicate a program's environment requirements within the portable desktop environment. The invention further provides a means for providing universal synchronization of a portable customized desktop, thereby preserving data and providing alternate access by User. | 08-20-2009 |
Hung O. Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090160411 | FAST VOLTAGE REGULATORS FOR CHARGE PUMPS - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 06-25-2009 |
| 20100142272 | METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP - In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC. | 06-10-2010 |
| 20110022905 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 01-27-2011 |
Hung T. Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080251019 | SYSTEM AND METHOD FOR TRANSFERRING A SUBSTRATE INTO AND OUT OF A REDUCED VOLUME CHAMBER ACCOMMODATING MULTIPLE SUBSTRATES - The present invention comprises a system and method for transferring a substrate into and out of a chamber configured to accommodate multiple substrates. In one embodiment, the system comprises a chamber housing that includes a first substrate support tray and a second substrate support tray independently movable along a vertical axis, and a substrate conveyor movable into and out of the chamber housing. The first substrate support tray and the second substrate support tray are movable to a position where a portion of the second substrate support tray is received in the first substrate support tray. | 10-16-2008 |
| 20090195262 | IN-LINE ELECTRON BEAM TEST SYSTEM - A method and apparatus for testing a plurality of electronic devices formed on a large area substrate is described. In one embodiment, the apparatus performs a test on the substrate in one linear axis in at least one chamber that is slightly wider than a dimension of the substrate to be tested. Clean room space and process time is minimized due to the smaller dimensions and volume of the system. | 08-06-2009 |
| 20100098518 | IN/OUT DOOR FOR A VACUUM CHAMBER - A load lock chamber sized for a large area substrate is provided. The load lock chamber includes a housing comprising a door and a body having at least two sealable ports, a movable door associated with at least one of the sealable ports, and a door actuation assembly coupled between the door and the housing. The door actuation assembly further includes a pair of first actuators coupled to the door for moving the door in a first direction, and a pair of second actuators for moving the door in a second direction that is orthogonal to the first direction. | 04-22-2010 |
| 20100327162 | IN-LINE ELECTRON BEAM TEST SYSTEM - A method and apparatus for testing a plurality of electronic devices formed on a large area substrate is described. In one embodiment, the apparatus performs a test on the substrate in one linear axis in at least one chamber that is slightly wider than a dimension of the substrate to be tested. Clean room space and process time is minimized due to the smaller dimensions and volume of the system. | 12-30-2010 |
Hungviet Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100111164 | Method and System for Data Management in a Video Decoder - A method and system for minimizing bus traffic in a video decoder is disclosed. A method and system for processing a portion of a reference picture includes designating the reference picture, selecting a display picture within the reference picture, transmitting a display picture size, and sending a display picture offset. A method and system for compressing IDCT coefficients corresponding to a macroblock, the macroblock having a plurality of blocks, includes locating each non-zero IDCT coefficient corresponding to one of the plurality of blocks, assigning an index to the non-zero IDCT coefficient, the index designating a location within the one of the plurality of blocks, packing the non-zero IDCT coefficient in little endian format, and specifying a terminator bit corresponding to the non-zero coefficient, the terminator bit indicating the end of all non-zero IDCT coefficients for the one of the plurality of blocks. A method and system for selectively controlling each hardware device within a video decoder includes obtaining a video stream, performing VLC decoding, encoding a plurality of instructions to control each hardware device within the video decoder, decoding each one of the plurality of instructions, and optionally performing an IDCT in response to each one of the plurality of instructions. | 05-06-2010 |
Richard C. Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120007221 | MASK FOR FORMING INTEGRATED CIRCUIT - A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask. | 01-12-2012 |
Sang Thanh Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080290931 | Charge pump systems and methods - Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry. | 11-27-2008 |
Tai Dung Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100190353 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 07-29-2010 |
| 20100285237 | NANOLAYER DEPOSITION USING BIAS POWER TREATMENT - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, comprising introducing a first plurality of precursors to deposit a thin layer with the deposition process not self limiting, followed by introducing a second plurality of precursors for plasma treating the thin deposited layer. The plasma can be isotropic, anisotropic, or a combination of isotropic and anisotropic to optimize the effectiveness of the treatment of the thin deposited layers. | 11-11-2010 |
Tam Dinh Thanh Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090325085 | STENCIL DESIGN AND METHOD FOR IMPROVING CHARACTER DENSITY FOR CELL PROJECTION CHARGED PARTICLE BEAM LITHOGRAPHY - The present invention increases the number of characters available on a stencil for charged particle beam lithography. A stencil for charged particle beam lithography is disclosed, comprising two character projection (CP) characters, wherein the blanking areas for the two CP characters overlap. A stencil is also disclosed comprising two CP characters with one or more optional characters between the two characters, wherein the optional characters can form meaningful patterns on a surface only in combination with one of the two characters. A stencil is also disclosed wherein the blanking area of a CP character extends beyond the boundary of the stencil's available character area. Methods for design of the aforementioned stencils are also disclosed. | 12-31-2009 |
| 20110278731 | METHOD FOR INTEGRATED CIRCUIT DESIGN AND MANUFACTURE USING DIAGONAL MINIMUM-WIDTH PATTERNS - Methods for designing and manufacturing an integrated circuit are disclosed, in which the physical design process for a standard cell or cells utilizes a preferred diagonal direction for minimum-width patterns on at least one layer, where the standard cell or cells are used in the layout of an integrated circuit. The methods also include forming the patterns on a photomask using model-based fracturing techniques with charged particle beam simulation, and forming the patterns on a substrate such a silicon wafer using the photomask and an optical lithographic process with directional illumination which is optimized for the preferred diagonal direction. | 11-17-2011 |
Thien T. Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080250261 | System and method for enabling functionality based on measured power - According to one embodiment of the invention, an apparatus comprises an input port, a measuring circuit and a processor. The measuring circuit is adapted to measure a power parameter associated with power supplied over a communication media to the input port. The processor includes a plurality of logic units. Each logic unit is configured to be activated in series to control power usage of the apparatus. | 10-09-2008 |
Tue Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100190353 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 07-29-2010 |
| 20100285237 | NANOLAYER DEPOSITION USING BIAS POWER TREATMENT - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, comprising introducing a first plurality of precursors to deposit a thin layer with the deposition process not self limiting, followed by introducing a second plurality of precursors for plasma treating the thin deposited layer. The plasma can be isotropic, anisotropic, or a combination of isotropic and anisotropic to optimize the effectiveness of the treatment of the thin deposited layers. | 11-11-2010 |
Van-Duc Nguyen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110260055 | Dynamic Focus Adjustment with Optical Height Detection Apparatus in Electron Beam system - The present invention generally relates to dynamic focus adjustment for an image system. With the assistance of a height detection sub-system, present invention provides an apparatus and methods for micro adjusting an image focusing according the specimen surface height variation by altering the field strength of an electrostatic lens between objective lens and sample stage/or a bias voltage applied to the sample surface. Merely by way of example, the invention has been applied to a scanning electron inspection system. But it would be recognized that the invention could apply to other system using charged particle beam as observation tool with a height detection apparatus. | 10-27-2011 |