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Nguyen, Cupertino
David Nguyen, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110119425 | DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM - The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module. | 05-19-2011 |
Hoanganh T. (ht) Nguyen, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110244435 | METHOD AND APPARATUS FOR IMPROVING MATH SKILLS - A method and apparatus for improving math skills is provided. The method and apparatus present groups of problems to a student in a sequential manner, and award points to the student when the student enters a correct response. Statistics regard the student's performance are recorded and may be viewed in a variety of selectable formats so that parents, teachers, and other interested parties can track the students progress. | 10-06-2011 |
Hung Thanh Nguyen, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090161465 | Non-volatile Memory Device Having High Speed Serial Interface - A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit. | 06-25-2009 |
| 20100067311 | Non-Volatile Memory Device Having High Speed Serial Interface - A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit. | 03-18-2010 |
Khanh B. Nguyen, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120036024 | MIXED AUCTIONS - In general, first bids associated with an ad request are identified, where the first bids have an auction value that is set at a bidding time. Second bids associated with the ad request are identified, where the second bids have an auction value that is unknown at the bidding time. One or more predicted auction values for the second bids are determined, and an auction is run to identify one or more winning bids from the first and second bids for satisfying the ad request. | 02-09-2012 |
Tam Minh Nguyen, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090161465 | Non-volatile Memory Device Having High Speed Serial Interface - A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit. | 06-25-2009 |
| 20100067311 | Non-Volatile Memory Device Having High Speed Serial Interface - A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit. | 03-18-2010 |
Tung M. Nguyen, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110055844 | HIGH DENSITY MULTI NODE COMPUTER WITH INTEGRATED SHARED RESOURCES - A multi-node computer system, comprising: a plurality of nodes, a system control unit and a carrier board. Each node of the plurality of nodes comprises a processor and a memory. The system control unit is responsible for: power management, cooling, workload provisioning, native storage servicing, and I/O. The carrier board comprises a system fabric and a plurality of electrical connections. The electrical connections provide the plurality of nodes with power, management controls, system connectivity between the system control unit and the plurality of nodes, and an external network connection to a user infrastructure. The system control unit and the carrier board provide integrated, shared resources for the plurality of nodes. The multi-node computer system is provided in a single enclosure. | 03-03-2011 |