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Nguyen, Austin
Chi Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100268925 | SYSTEM AND METHOD FOR POPULATING A DEDICATED SYSTEM SERVICE REPOSITORY FOR AN INFORMATION HANDLING SYSTEM - An information handling system includes a processor, a memory device coupled to the processor, and a dedicated system service repository (DSSR) coupled to the processor. The DSSR is configured to store a base image that includes a plurality of partitions and a first system configuration image, wherein the first system configuration image is stored in a first partition of the plurality of partitions, wherein the first system configuration image is configured to provide in-band and/or out-of-band managed access to the DSSR when executed; and by accessing the first system configuration image, the DSSR is populated with a second system configuration image, wherein the second system configuration image is stored in a second partition of the plurality of partitions. | 10-21-2010 |
Chung T. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120119881 | INFORMATION MANAGEMENT USING A CUSTOM IDENTIFIER STORED ON AN IDENTIFICATION TAG - A solution for managing information using an identification tag is provided. For example, information relating to an item and/or one or more transfers of the item can be managed using an identification tag associated with the item. The identification tag can store and transmit an item identifier, such as an electronic product code (EPC), corresponding to the item, which can be obtained and stored in a data store. Access information for retrieving the item identifier and identification information for a party to the transfer can be used to generate a custom identifier that can be provided for storage on the identification tag in place of the item identifier. The custom identifier can subsequently be used to acquire information on the item and/or the transfer event. | 05-17-2012 |
Cuong Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090077208 | System And Method For Assigning Addresses To Information Handling Systems - Information handling system network addresses are managed to support a consistent MAC address for iSCSI and fibre channel host bus adapter. For example, a management controller retrieves a MAC address from persistent memory, such as a network location, and assigns the MAC address to a non-persistent memory of a predetermined information handling system network component so that the MAC address remains consistent even if the network component is replaced. For example, an offload engine that supports network communications with iSCSI receives a MAC address from a network location and applies the MAC address for use by a host bus adapter. Alternatively, an offload engine supports Fibre Channel with World Wide Name or World Wide Identifier address assignments. | 03-19-2009 |
Cuong T. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080198749 | Technique for handling service requests in an information handling system - A technique for handling a service request in an information handling system includes receiving, at a data link layer device, a packet transmitted from a client, the data link layer device including multiple ports. The packet is examined to determine whether the packet includes a first-type request. The packet is then routed to a server via a trusted port, included within the multiple ports, when the packet includes the first-type request. | 08-21-2008 |
| 20090119322 | SYSTEM AND METHOD FOR MANAGING CONTENT - A system for managing media files having different format characteristics includes a transcoder, a content store, and a plurality of clients. The content store is capable of storing a media file in a first format. The clients are each associated with one or more media file formats and capable of playing media files to users. The transcoder is capable of receiving a request identifying a media file from a first client and, in response to receiving the request, retrieving the media file from the content store in a first format. The transcoder is also operable of modifying the media file from the first format to a second format associated with the first client and, while modifying the media file from the first format to the second format, transmitting a modified portion of the media file to the first client. | 05-07-2009 |
| 20100094931 | SYSTEM AND METHOD FOR PROGRESSIVE DELIVERY OF MEDIA CONTENT - A method for delivering media content includes receiving a request for media content from a client and identifying a first media file containing media content associated with the request. The first file has a first media format. The method further includes initiating creation of a second media file associated with the request and estimating one or more characteristic of the second media file. The second media file has a second media format. Additionally, the method includes generating media information for the second media file based on the estimated characteristics of the second media file and transmitting the media information to the client before creation of the second media file has been completed. | 04-15-2010 |
| 20100185776 | SYSTEM AND METHOD FOR SPLICING MEDIA FILES - A method for processing media content includes receiving a request for media content and, in response to receiving the request, accessing a plurality of source files associated with the requested media content, wherein the source files comprise media content in one or more source formats. The method also includes generating one or more target files based on the plurality of source files. The target files include media content in a target format. Additionally, the method includes, generating an auxiliary file associated with the target files while generating the target files. The auxiliary file includes a plurality of content records. Each content record is associated with a portion of the media content in the target files and indicates a location of the associated portion of the media content in a particular one of the target files. The method further includes, while generating the target files, transmitting the requested media content from the plurality of target files to a client as a seamless media transmission by reading each of the content records in the auxiliary file and transmitting to the client content corresponding to each content record. | 07-22-2010 |
Giang Chau Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090077441 | METHOD AND APPARATUS FOR SCHEDULING TEST VECTORS IN A MULTIPLE CORE INTEGRATED CIRCUIT - A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector. | 03-19-2009 |
| 20120032716 | Initializing Components of an Integrated Circuit - Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component. | 02-09-2012 |
Hai Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090242125 | Carrier Head Membrane - A method and apparatus for planarizing a substrate are provided. A substrate carrier head with an improved cover for holding the substrate securely is provided. The cover may have a bead that is larger than the recess into which it fits, such that the compression forms a conformal seal inside the recess. The bead may also be left uncoated to enhance adhesion of the bead to the surface of the groove. The surface of the cover may be roughened to reduce adhesion of the substrate to the cover without using a non-stick coating. | 10-01-2009 |
Hoa Cong Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080201710 | METHOD AND SYSTEM FOR MANAGING PERIPHERAL CONNECTION WAKEUP IN A PROCESSING SYSTEM SUPPORTING MULTIPLE VIRTUAL MACHINES - A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection. | 08-21-2008 |
Huy B. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080279029 | LOW VOLTAGE DATA PATH IN MEMORY ARRAY - A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch. | 11-13-2008 |
| 20090213668 | ADJUSTABLE PIPELINE IN A MEMORY CIRCUIT - A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon. | 08-27-2009 |
| 20120033520 | MEMORY WITH LOW VOLTAGE MODE OPERATION - A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells. | 02-09-2012 |
Long V. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110080904 | Subscriber Line Interface Circuitry with POTS Detection - A method of controlling a subscriber line interface circuit (SLIC) includes performing a plain old telephone services (POTS) detect at a customer premises using a customer premises SLIC. Injection of POTS services by the customer premises SLIC is disabled, if POTS is detected. | 04-07-2011 |
Minh Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120084768 | Capturing Multi-Disk Virtual Machine Images Automatically - A plurality of virtual disk images are established on a virtual machine. The virtual machine identifies corresponding network address translations for a plurality of disks, each having a corresponding plurality of data sets. The virtual machine installs the corresponding plurality of data sets to the plurality of virtual disks using the corresponding network address translations. An image of the plurality of disks is created, wherein the image contains the plurality of virtual disks with the plurality of data sets. | 04-05-2012 |
Nga K. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100279543 | COLD-SHRINK SEPARABLE CONNECTOR - A cold-shrink article having a chamber with an enlarged interior section to prevent the collapse of an end of a support core placed in the chamber. | 11-04-2010 |
Paul Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080291835 | METHOD AND APPARATUS FOR MANAGING BUFFERS FOR TRANSMITTING PACKETS - A computer implemented method, apparatus, and computer usable program code for managing buffers. A number of buffers present in a pool of buffers assigned to a network device driver are monitored, wherein the buffers in the pool of buffers are used to process packets of data for transmission onto a network. A request is denied from a transport layer for a buffer from the pool of buffers if the number of buffers falls below a threshold level, wherein at least one buffer is present in a buffer pool if the number of buffers falls below the threshold level. | 11-27-2008 |
Quoc P. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110048721 | DI-FUNCTIONAL SURFACTANTS FOR ENHANCED OIL RECOVERY - The present invention describes the synthesis and use of cleavable di-functional anionic surfactants for enhanced oil recovery applications and/or the use of sacrificial surfactants. | 03-03-2011 |
| 20110059872 | COMPOSITIONS AND METHODS FOR CONTROLLING THE STABILITY OF ETHERSULFATE SURFACTANTS AT ELEVATED TEMPERATURES - The present invention describes the method of making an ether sulfate surfactant solution hydrolytically stable by adding one or more alkalinity generating agents at levels greater than 0.05%. The surfactant solutions of the present invention have half-lives >8 months at 100° C. and find uses in EOR applications, environmental cleanups, detergent industry, and any other surfactant based high temperature applications. | 03-10-2011 |
| 20110071057 | METHOD OF MANUFACTURE AND USE OF LARGE HYDROPHOBE ETHER SULFATE SURFACTANTS IN ENHANCED OIL RECOVERY (EOR) APPLICATIONS - The present invention describes the method of making anionic ether sulfate surfactants by alkoxylation of a GA using PO and/or EO followed by a sulfation reaction. The GA of the present invention is made by a facile and inexpensive method that involves high temperature base catalyzed dimerization of a linear alcohol. The ether sulfate surfactants of the present invention find uses in EOR applications where it is used for solubilization and mobilization of oil and for environmental cleanup. | 03-24-2011 |
Thang Q. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100318716 | ORDERED QUEUE AND METHODS THEREFOR - A device receives a first request from a requesting device for first information that is stored at contiguous address locations beginning at a first address. A plurality of spawned requests are generated that each request a different portion of the first information. A table location is allocated to each one of the plurality of requests, wherein the relative location of each allocated table location is indicative of an order that the information from each spawned request is to be returned to the requesting device relative to the information from each other spawned request. | 12-16-2010 |
| 20110107065 | INTERCONNECT CONTROLLER FOR A DATA PROCESSING DEVICE AND METHOD THEREFOR - A data processing device includes an interconnect controller operable to manage the communication of information between modules of the data processing device via an interconnect. In response to a transaction request the interconnect controller selects a tag value from a set of available tag values, assigns the tag to the transaction and reserves the tag value so that it is unavailable for assignment to other transactions. If an expected response to the transaction request is not received within a designated amount of time, the transaction enters a timed-out state and the interconnect controller locks the tag value, so that it remains unavailable for assignment to other transactions until an unlock event, such as a request from software. | 05-05-2011 |
Thanh Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120079256 | Interrupt suppression - A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts are being received to a threshold rate. In response to determining that the rate at which the interrupts are being received is greater than the threshold rate, the processor sends just the first received interrupt to firmware for processing. All other of the interrupts are not sent from the processor to the firmware but instead are suppressed by the processor. By comparison, in response to determining that the rate at which the interrupts are being received is less than the threshold rate, the processor can send all the interrupts from the processor to firmware for processing. | 03-29-2012 |
Thoi Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080201710 | METHOD AND SYSTEM FOR MANAGING PERIPHERAL CONNECTION WAKEUP IN A PROCESSING SYSTEM SUPPORTING MULTIPLE VIRTUAL MACHINES - A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection. | 08-21-2008 |
Tuyet-Huong T. Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080307273 | System And Method For Predictive Failure Detection - A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period. | 12-11-2008 |
Tuyet-Huong Thi Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100306768 | Methods for Managing Performance States in an Information Handling System - An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS. | 12-02-2010 |
Yen Teresa Nguyen, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090052336 | Ethernet Switch With Configurable Alarms - According to one embodiment, an Ethernet switch includes a plurality of ports operable to receive and transmit Ethernet traffic. The Ethernet switch also includes system monitoring software operable to receive an indication from a user of a plurality of fault conditions for which generation of an alarm is desired. The system monitoring software is also operable to monitor the Ethernet switch for the plurality of fault conditions and generate a signal indicating a particular one of the plurality of fault conditions has occurred. The Ethernet switch further includes at least one relay responsive to the generated signal that is operable to turn on a respective alarm indicating a particular fault condition has occurred. | 02-26-2009 |