| Patent application number | Description | Published |
|---|
| 20080201531 | STRUCTURE FOR ADMINISTERING AN ACCESS CONFLICT IN A COMPUTER MEMORY CACHE - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure includes an apparatus for administering an access conflict in a cache. The apparatus includes the cache, a cache controller, and a superscalar computer processor. The cache controller is capable of receiving a write address and write data from the superscalar computer processor's store memory instruction execution unit and a read address for read data from the superscalar computer processor's load memory instruction execution unit, for writing and reading data from a same cache line in the cache simultaneously on a current clock cycle; storing the write data in the same cache line on the current clock cycle; stalling, in the load memory instruction execution unit, a corresponding load microinstruction; and reading from the cache on a subsequent clock cycle read data from the read address. | 08-21-2008 |
| 20080209131 | STRUCTURES, SYSTEMS AND ARRANGEMENTS FOR CACHE MANAGEMENT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processing system. The process system generally includes a processor, cache coupled to the processor to provide at least one line of binary storage to the processor module, an eviction management module coupled to the processor to monitor lines of code interacting with the cache and to count storage related occurrences of the lines of code with respect to the cache, the lines of code having an identifier, and a cache directory to store the count and the identifier, wherein if processor requests cache capacity, the cache directory provides eviction related data for a line of code stored in the cache to the processor. | 08-28-2008 |
| 20080215818 | STRUCTURE FOR SILENT INVALID STATE TRANSITION HANDLING IN AN SMP ENVIRONMENT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line. | 09-04-2008 |
| 20080235452 | DESIGN STRUCTURE FOR SHARED CACHE EVICTION - A design structure embodied in a machine readable storage medium for of designing, manufacturing, and/or testing for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores is provided. The design structure includes means for receiving from a processor core a request to load a cache line in the shared cache; means for determining whether the shared cache is full; means for determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and means for evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache. | 09-25-2008 |
| 20080313427 | DIRECTORY-BASED DATA TRANSFER PROTOCOL FOR MULTIPROCESSOR SYSTEM - A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state. | 12-18-2008 |
| 20090019233 | STRUCTURE FOR DYNAMIC INITIAL CACHE LINE COHERENCY STATE ASSIGNMENT IN MULTI-PROCESSOR SYSTEMS - A design structure embodied in a machine readable storage medium for designing, manufacturing, and testing a system for providing lines of data from shared resources to caching agents are provided. The system provides for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data. | 01-15-2009 |
| 20090037664 | SYSTEM AND METHOD FOR DYNAMICALLY SELECTING THE FETCH PATH OF DATA FOR IMPROVING PROCESSOR PERFORMANCE - A system and method for dynamically selecting the data fetch path for improving the performance of the system improves data access latency by dynamically adjusting data fetch paths based on application data fetch characteristics. The application data fetch characteristics are determined through the use of a hit/miss tracker. It reduces data access latency for applications that have a low data reuse rate (streaming audio, video, multimedia, games, etc.) which will improve overall application performance. It is dynamic in a sense that at any point in time when the cache hit rate becomes reasonable (defined parameter), the normal cache lookup operations will resume. The system utilizes a hit/miss tracker which tracks the hits/misses against a cache and, if the miss rate surpasses a prespecified rate or matches an application profile, the hit/miss tracker causes the cache to be bypassed and the data is pulled from main memory or another cache thereby improving overall application performance. | 02-05-2009 |
| 20090157970 | METHOD AND SYSTEM FOR INTELLIGENT AND DYNAMIC CACHE REPLACEMENT MANAGEMENT BASED ON EFFICIENT USE OF CACHE FOR INDIVIDUAL PROCESSOR CORE - Determining and applying a cache replacement policy for a computer application running in a computer processing system is accomplished by receiving a processor core data request, adding bits on each cache line of a plurality of cache lines to identify a core ID of an at least one processor core that provides each cache line in a shared cache, allocating a tag table for each processor core, where the tag table keeps track of an index of processor core miss rates, and setting a threshold to define a level of cache usefulness, depending on whether or not the index of processor core miss rates exceeds the threshold. Checking the threshold and when the threshold is not exceeded, then a shared cache standard policy for cache replacement is applied. When the threshold is exceeded, then the cache line from the processor core running the application is evicted from the shared cache. | 06-18-2009 |
| 20100325367 | Write-Back Coherency Data Cache for Resolving Read/Write Conflicts - A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is cached in a write-back cache located in a memory controller hardware. The write-back cache holds data being written back to main memory for a period of time prior to writing the data to main memory. If the data is cached in the write-back cache, the data is removed from the write-back cache and forwarded to the requesting processor. The cache coherency state in the coherency directory entry for the data is updated to reflect the current cache coherency state of the data based on the requesting processor's intended use of the data. | 12-23-2010 |
